An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vol+ and Vol; and an output alignment circuit configured to output voltages Vo+ and Vo that are triggered by an edge of a combination of Vol+ and Vol, and where Vo+ and Vo are set by high states of Vol+ and Vol prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vol+ and Vol; and outputting, by an output alignment circuit, voltages Vo+ and Vo that are triggered by an edge of a combination of Vol+ and Vol, and where Vo+ and Vo are set by high states of Vol+ and Vol prior to a transition on an input of the level-shifter circuit.

A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory.

An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vol+ and Vol; and an output alignment circuit configured to output voltages Vo+ and Vo that are triggered by an edge of a combination of Vol+ and Vol, and where Vo+ and Vo are set by high states of Vol+ and Vol prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vol+ and Vol; and outputting, by an output alignment circuit, voltages Vo+ and Vo that are triggered by an edge of a combination of Vol+ and Vol, and where Vo+ and Vo are set by high states of Vol+ and Vol prior to a transition on an input of the level-shifter circuit.

Provided is a circuit device including: a first terminal electrically coupled to one end of a vibrator; a second terminal electrically coupled to the other end of the vibrator; an oscillation circuit electrically coupled to the first terminal and the second terminal, and oscillating the vibrator; a third terminal to which an external input signal is input; a switch circuit provided between a first wiring which couples the first terminal and the oscillation circuit with each other and the third terminal, and having a P-type transistor; and a control circuit outputting a regulated voltage, in which a power supply voltage is regulated, as a substrate voltage of the P-type transistor.

An isolated switched-mode power converter converts power from an input source into power for an output load. A digital controller senses a secondary-side voltage, such as a rectified voltage, of the power converter. The secondary-side voltage is divided down using a high-impedance voltage divider. The resultant divided-down voltage is provided to a voltage sensor within the digital controller. The voltage sensor level shifts the provided voltage, and buffers the resulting level-shifted voltage. The buffered, level-shifted voltage is provided to a tracking analog-to-digital converter (ADC) for digitization. The buffered signal provided to the tracking ADC has a high current capability, such that the voltage input to the tracking ADC may quickly converge before the tracking ADC outputs a digital value for the sensed secondary-side voltage.

An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vo1+ and Vo1; and an output alignment circuit configured to output voltages Vo+ and Vo that are triggered by an edge of a combination of Vo1+ and Vo1, and where Vo+ and Vo are set by high states of Vo1+ and Vo1 prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vo1+ and Vo1; and outputting, by an output alignment circuit, voltages Vo+ and Vo that are triggered by an edge of a combination of Vo1+ and Vo1, and where Vo+ and Vo are set by high states of Vo1+ and Vo1 prior to a transition on an input of the level-shifter circuit.

A memory cell includes a first anti-fuse element, a second anti-fuse element, and a selection circuit. The first anti-fuse element has a first terminal, a second terminal being floating, and a control terminal coupled to a first anti-fuse control line. The second anti-fuse element has a first terminal coupled to the first terminal of the first anti-fuse element, a second terminal being floating, and a control terminal coupled to a second anti-fuse control line. The selection circuit is coupled to the first terminal of the first anti-fuse element, the first terminal of the second anti-fuse element, and a source line. The selection circuit controls an electrical connection from the source line to the first terminal of the first anti-fuse element and the first terminal of the second anti-fuse element.

A circuit for driving a switched transistor comprises: a level shifter comprising at least one transistor, the level shifter configured to convert an input pulse to a pulse having a greater voltage swing than the input pulse and shift a voltage level of the converted pulse; and a pulse shaping filter coupled between the level shifter and the gate of the switched transistor, the pulse shaping filter tuned to cancel or reduce an impedance of the gate of the switched transistor. The switched transistor and/or the at least one transistor are a GaN High Electron Mobility Transistor (HEMT).

A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.

A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage V.sub.ON and the turn-off voltage V.sub.D to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.