In certain aspects of the disclosure, an apparatus comprises a latching element having a data input, a first feedback input, a second feedback input, and an output. A pull-up input block is coupled to the data input and has at least a first pull-up input, and a pull-down input block is also coupled to the data input and has at least a first pull-down input. A feedback pull-down block implementing a logic function complementary to the pull-up input block is coupled to a feedback pull-down control device and responsive to the first pull-up input, and a feedback pull-up block implementing a logic function complementary to the pull-down input block is coupled to a feedback pull-up control device and responsive to the first pull-down input. The pull-up input block and pull-down input block are guaranteed not to be enabled concurrently.

A low voltage differential signaling circuit includes an output driver circuit configured to provide a differential signal pair based on a first signal and a second signal. A peak detect circuit is coupled to receive the differential signal pair and configured to provide a feedback signal based on the differential signal pair and the first and second signals. An amplifier circuit has a first input coupled to the peak detect circuit, a second input coupled to receive a reference voltage, and an output coupled to provide a bias voltage to the output driver circuit.

A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

Inventive aspects include a dynamic flip flop, comprising a data independent P-stack feedback circuit. The data independent P-stack feedback circuit may include a first P-type transistor gated by a first dynamic inverted net signal, and a second P-type transistor gated by an inverted clock signal. A drain of the second P-type transistor may be coupled to a source of the first P-type transistor. A source of the second P-type transistor may be coupled to a node that is configured to receive a second dynamic inverted net signal. The source of the second P-type transistor may be directly coupled to the node that is configured to receive the second dynamic inverted net signal instead of a constant power source. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.

A latch and an isolation circuit are provided. The latch includes a first-level substructure and at least one second-level substructure, the number of the at least one second-level substructure is k, and k is a positive integer greater than or equal to 1. The first-level substructure includes a first load having a first terminal coupled with a first port, a second load having a first terminal coupled with the first port, a first driving circuit having a control terminal coupled with a second terminal of the first load and a second terminal coupled with a second port, a second driving circuit having a control terminal coupled with a second terminal of the second load and a second terminal coupled with the second port. Each of the at least one second-level substructure includes a third load, a fourth load, a third driving circuit and a fourth driving circuit.

A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.

A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.

In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.