Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.

A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.

Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.

A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a differential logical output. During a normal operational mode, the DSFF is synchronized by a clock signal to provide a differential logical output in a differential output state in accordance with a data input or in a precharge state based on the clock signal. The differential logical output is provided in a differential output state in accordance with a test input during a scan mode. The CDC is configured to generate a test enable input during the scan mode that indicates the scan mode once the differential logical output is in the differential output state. Accordingly, another SSE can be asynchronously triggered to operate in the scan mode without a separate scan clock.

A Schmitt trigger circuit includes a first circuit; a second circuit; a first switch; a third circuit; and a second switch. The first circuit output the output signal of a second or first logical level. The second circuit is coupled to a first potential node at a first end, and sends a current between the first end and a second end based on the output signal. The first switch electrically couples or uncouples the second end and a first node based on a selection signal. The third circuit is coupled to a second potential node at a third end, and sends a current exclusively with the second circuit between the third end and a fourth end based on the output signal. The second switch electrically couples or uncouples the fourth end and the first node based on the selection signal.

A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.

A Schmitt trigger circuit includes a first circuit; a second circuit; a first switch; a third circuit; and a second switch. The first circuit output the output signal of a second or first logical level. The second circuit is coupled to a first potential node at a first end, and sends a current between the first end and a second end based on the output signal. The first switch electrically couples or uncouples the second end and a first node based on a selection signal. The third circuit is coupled to a second potential node at a third end, and sends a current exclusively with the second circuit between the third end and a fourth end based on the output signal. The second switch electrically couples or uncouples the fourth end and the first node based on the selection signal.

A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.