A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

A buffer circuit includes a transistor cascode circuit, a latch circuit, a first transistor, a second transistor, and a voltage generator. The transistor cascode circuit is biasing at a first voltage. The latch circuit is biasing at a second voltage, whose voltage level is negative. The first transistor and the second transistor are coupling between the transistor cascode circuit and the latch circuit, and a gate of the first transistor is coupled to a gate of the second transistor. The voltage generator provides a biasing voltage to the gate of the first transistor and adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage. The biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters the steady state.

Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

A pulse generation circuit is configured with a plurality of transistors of a single conductivity type. The pulse generation circuit includes: an output unit including a current limiting element configured to supply, by a predetermined current, a first voltage from a first power supply line supplied with the first voltage to an output terminal, the output unit being configured to perform a bootstrap operation that outputs the first voltage to the output terminal in response to a received input signal; and an output control unit configured to initiate the bootstrap operation when the output terminal transitions to the first voltage, and after the output terminal transitions to the first voltage, terminate the bootstrap operation and perform control so as to output the first voltage from the current limiting element to the output terminal.

A novel PLL is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits. A first terminal of each of the first and second circuits is electrically connected to an output terminal of the i-th inverter. A second terminal of each of the first and second circuits is electrically connected to an input terminal of the (i+1)-th inverter. The first circuit has functions of storing first data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the first data. The second circuit has functions of storing second data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the second data.

A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

A data retention circuit includes a flip-flop circuit including a master latch coupled to a slave latch, wherein the slave latch includes a first input terminal and a first output terminal, and a series combination of a retention latch and a level shifter coupled between the first input terminal and the first output terminal. The slave latch is configured to be selectively coupled to the series combination through a first transmission gate responsive to a restore signal.

A circuit includes a first power node having a first voltage level, a second power node having a second voltage level different from the first voltage level, a reference node having a reference voltage level, a master latch that outputs a first bit based on a received bit, a slave latch that outputs a second bit based on the first bit and an output bit based on a selected one of the first bit or a third bit, a first level shifter that outputs the third bit based on a complementary bit pair, and a retention latch including a second level shifter and a pair of inverters that outputs the complementary bit pair based on the second bit. The slave latch and the first level shifter are coupled between the first power and reference nodes, and the retention latch is coupled between the second power and reference nodes.

An apparatus may include a first node coupled to a first terminal, the first terminal to receive a first control signal; a second node coupled to a second terminal, the second terminal to receive a second control signal; a first capacitor having a first plate coupled to the first node and a second plate coupled to a first output terminal; a second capacitor having a first plate coupled to the second node and a second plate coupled to a second output terminal; a first stack of transistors coupled between a positive supply terminal and a common mode terminal, the first stack operable to divide voltage; and a second stack of transistors coupled between a negative supply terminal and the common mode terminal, the second stack operable to divide voltage.