Disclosed examples include ICs and general-purpose I/O circuitry to facilitate interfacing of the IC with a variety of external circuits operating at different supply voltages, in which an integer number N supply drive circuits are individually coupled with a corresponding supply voltage node and selectively connect the corresponding supply voltage node to a general-purpose output node based on a supply drive control signal to allow programmable interfacing of individual general-purpose output pads or pins of the IC with an external circuit at the appropriate signal level.

Disclosed is a fault event detector configured to detect a fault injection event in an area of a chip that includes a vulnerable digital circuit. Such a fault event detector may include a bistable device that changes state at least partially in response to a presence of a fault injection event in a surrounding area of the fault event detector. Such a fault event detector may be arranged relative to a vulnerable digital circuit such that the vulnerable digital circuit is substantially located within the surrounding area of the first fault event detector.

A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

A flip-flop circuit includes gate circuits of which the number is N being an integer of 3 or more, and in which an output signal from the (N−1)th gate circuit is used as an input signal of the N-th gate circuit, the gate circuit being configured to output the output signal in response to a clock signal and the input signal. The N gate circuits include a first MOS transistor group including MOS transistors which are in an OFF state when a potential of an output signal node that outputs the output signal is held, and a second MOS transistor group including MOS transistors which are in an ON state when the potential of the output signal node is held. A threshold voltage of at least one MOS transistor in the first MOS transistor group is higher than a threshold voltage of at least one MOS transistor in the second MOS transistor group.

A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

In example implementations, an apparatus is provided. The apparatus includes a first low voltage control block, a second low voltage control block, a primitive level shifter coupled to the first low voltage control block, a plurality of nozzle level shifters coupled to the primitive level shifter and a second low voltage control block, and a high side switch (HSS) control coupled to each one of the plurality of nozzle level shifters and the second low voltage control block. The plurality of nozzle level shifters are communicatively coupled to each other. The primitive shifter is to enable a selected nozzle level shifter to fire a respective HSS control circuit of the selected nozzle level shifter and to direct a tail current from the selected nozzle level shifter.

A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.