An assembly includes a signal input, a signal output, a pull-up stack coupled to the signal input and to the signal output, a pull-down stack coupled to the signal input and to the signal output, and a hysteresis assembly coupled to the pull-up stack and to the pull-down stack. The pull-up stack comprises a pair of metal oxide semiconductor field-effect transistors (transistors) coupled in series, each transistor of the pair of transistors comprising a gate coupled to the signal input. The pull-down stack comprises a plurality of transistors coupled in series, the plurality of transistors comprising: a first transistor comprising a gate coupled to the signal input, a second transistor comprising a gate coupled to the signal input, and a third transistor. The hysteresis assembly comprises a pair of transistors, each transistor of the pair of transistors of the hysteresis assembly having a gate coupled to the signal output.

An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.

An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.

A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.

A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.

An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.

A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.