H03K2005/00045

Phase noise measurement and filtering circuit

Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.

Voltage Comparator Circuit Including a Plurality of Voltage Controlled Delay Lines
20180198440 · 2018-07-12 ·

An embodiment circuit includes a first voltage-controlled delay line (VCDL), a second VCDL, and a first flip-flop. The first VCDL includes a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal. The second VCDL includes a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal. The first flip-flop includes a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL.

METHOD AND DEVICE FOR DATA TRANSMISSION AND COUNTER UNIT
20180102810 · 2018-04-12 · ·

The method is used for transmitting signals and data within at least one first and one second transmission phase (TP1, TP2), which follow one another synchronously or asynchronously, between a first communication unit (L) and at least one second communication unit (Z), which comprises a central processor unit (CPU), a memory unit (M), in which an operating program (OP) is stored, and at least one first event generator (EG1), which monitors signal sequences (SL, SZ) transmitted via a transmission line (W) between the two communication units (L, Z) independently of the central processor unit (CPU) and generates event notifications (e1, e2) for events during the data transmission, which occur in accordance with the applied transmission protocol, which event notifications are transmitted to the central processor unit (CPU) and/or to at least one event user (EU1).

PHASE NOISE MEASUREMENT AND FILTERING CIRCUIT
20170264261 · 2017-09-14 · ·

Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.

Phase noise measurement and filtering circuit

Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.

Electronically variable analog delay line
09559663 · 2017-01-31 · ·

An electronically variable analog delay line including at least one segment with an electronically variable inductance. The at least one segment includes a signal path, a ground return path, and a plurality of switches configured to vary the inductance of the segment.