An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

The invention relates to a pulse shaper (18). The pulse shaper (18) comprises an integrator (19) for generating a pulse having a peak amplitude indicative of the energy of a detected photon, a feedback resistor (22), switchable discharge circuitry (23) for discharging the integrator (19), and a peak detector (24) for detecting the peak of the pulse. The pulse shaper is adapted to start the discharge of the integrator by the switchable discharge circuitry based on the detection of the peak and to connect the feedback resistor in parallel to the integrator during a period of the pulse generation and to disconnect the feedback resistor during another period of the pulse generation. The pulse shaper can be such that the generation of the pulse is substantially unhindered by any noticeable concurrent discharging mechanism while, at the same time, the occurrence of energy pedestals can be efficiently avoided.

Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.