A timing adjustment method for a drive circuit, including: a rise detector for a rise start when a voltage-driven semiconductor element is turned off; a timing signal output unit outputting a speed change timing signal after a set delay time has elapsed from the rise start; and a conduction controller for a conduction control terminal of the semiconductor element using the timing signal, comprises: defining an estimated terminal voltage of the conduction control terminal when a rise completion time elapses; increasing a delay time by a predetermined unit time, and changing the drive signal to a turning off level again, when the conduction control terminal doesn't fall below the estimated terminal voltage after the drive signal is changed to a turning off level before the level is inverted; and determining a delay time, when the conduction control terminal falls below the estimated terminal voltage initially, as a set value.

An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.

A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.

Apparatuses, systems, and methods for a time domain voltage reference with zero quiescent current consumption are provided. An exemplary method includes outputting a first delay signal having a first delay that is based on an input voltage; outputting a second delay signal having a second delay that is based on a first voltage difference between the input voltage and an analog reference voltage; outputting first command signals that are based on a first time difference between the first delay and the second delay, wherein the first time difference corresponds to the first voltage difference; outputting a first counter signal indicative of a first value of a count of the counter, wherein the first value is based on the first command signals; and storing the first value, wherein a first programmable voltage delay line is configured to use the first value as a digital reference corresponding to the analog reference voltage.