A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.

A broadband impulse generator includes a first delay line and a second delay line that receive an input signal and include a plurality of delay elements connected in series with each other, an oscillation signal generator that generates an oscillation signal having a certain number of pulses during a target impulse duration based on the input signal and an output signal of the first delay line, an envelope signal generator that generates a plurality of envelope signals having a delay duration with each other and having a certain voltage level during the target impulse duration, based on the input signal and an output signal of the second delay line, and an impulse signal generator that generates an impulse signal having the certain number of pulses during the target impulse duration based on the plurality of impulse signals and the oscillation signal.

A first inverter in a clock generation circuit is coupled to an input clock signal and has multiple driver slices. Each driver slice includes first transistors that have gates coupled to the input clock signal, second transistors that have sources coupled to rails of a power supply. Each of the second transistors has a drain coupled to a source of one of the first transistors. The second transistors are turned on or turned off based on signaling state of a differential enable signal. A tuning resistor is coupled to the drains of the first transistors and further coupled to an output of the first inverter. A second inverter outputs a quadrature version of the input clock signal and has an input coupled to the output of the first inverter. A first tunable capacitor is coupled to the output of the first inverter.

A programmable delay device providing a delay resolution of less than 1 ns and a maximum delay of >100 ns over a broad bandwidth is disclosed. The device includes an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements. The programmable delay stage includes a total of MN delay switched capacitor storage elements, reducing the sampling rate by MN. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. The sampling clocks for the input and output reconstruction stages are independent, allowing a delay resolution corresponding to the sampling rate.