Patent classifications
H
ELECTRICITY
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H03
ELECTRONIC CIRCUITRY
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H03K
PULSE TECHNIQUE
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5/00
Manipulating of pulses not covered by one of the other main groups of this subclass
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H03K2005/00013
Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
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H03K2005/00097
Avoiding variations of delay using feedback, e.g. controlled by a PLL
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H03K2005/00104
using a reference signal, e.g. a reference clock
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H03K2005/00104

Pulse generator and method
12425010 · 2025-09-23 · ·

A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.

PULSE GENERATOR AND METHOD
20260012165 · 2026-01-08 · ·

A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.