A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor R.sub.S.

A circuit for generating a time delay, including a capacitive element for integrating a first current supplied by a first current source, in which the first current source includes a switched-capacitor circuit.

A current mirror calibration circuit, coupled to an error amplifier of a pulse-width modulation controller, includes a first voltage generation unit, a second voltage generation unit, a calibration unit and a current mirror circuit. During an initial period, the first voltage generation unit and second voltage generation unit provide a first default voltage and a second default voltage respectively. The current mirror circuit includes a first current unit and a second current unit. The first current unit receives an original current. The second current unit generates a mirror current having a proportional relationship with original current. The first current unit has a first node coupled to the first voltage generation unit and a second node coupled to a third default voltage. The second current unit has a third node coupled to the second voltage generation unit and calibration unit and a fourth node coupled to calibration unit and an output terminal of error amplifier.

A current mirror calibration circuit, coupled to an error amplifier of a pulse-width modulation controller, includes a first voltage generation unit, a second voltage generation unit, a calibration unit and a current mirror circuit. During an initial period, the first voltage generation unit and second voltage generation unit provide a first default voltage and a second default voltage respectively. The current mirror circuit includes a first current unit and a second current unit. The first current unit receives an original current. The second current unit generates a mirror current having a proportional relationship with original current. The first current unit has a first node coupled to the first voltage generation unit and a second node coupled to a third default voltage. The second current unit has a third node coupled to the second voltage generation unit and calibration unit and a fourth node coupled to calibration unit and an output terminal of error amplifier.

Systems and methods are provided for a delay line circuit that comprises a delay line core and a first current mirror circuit. The delay line core includes a plurality of inverters connected in series. Each of the plurality of inverters is coupled to a first common node. The first current mirror circuit includes a first current source configured to generate a first digital-to-analog (DAC) current, a first transistor coupled to the first current source, and a plurality of first controlling transistors coupled to the first transistor and the first common node. The plurality of first controlling transistors generates a first mirror current at the first common node based on the first DAC current. A delay time of the delay line core is controlled based on the first mirror current.

A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.

Systems and methods are provided for a delay line circuit that comprises a delay line core and a first current mirror circuit. The delay line core includes a plurality of inverters connected in series. Each of the plurality of inverters is coupled to a first common node. The first current mirror circuit includes a first current source configured to generate a first digital-to-analog (DAC) current, a first transistor coupled to the first current source, and a plurality of first controlling transistors coupled to the first transistor and the first common node. The plurality of first controlling transistors generates a first mirror current at the first common node based on the first DAC current. A delay time of the delay line core is controlled based on the first mirror current.

In some examples, a circuit includes a window comparator circuit. The window comparator circuit is configured to receive a input signal and a feedback signal, determine a delayed representation of the feedback signal based on a window control signal, determine, based on the feedback signal and the delayed representation of the feedback signal, a time window, responsive to a rising edge of the input signal occurring in the time window, or responsive to a falling edge of the input signal occurring in the time window, determine that the input signal and the feedback signal are locked, and responsive to the rising edge of the input signal occurring outside of the time window, or responsive to the falling edge of the input signal occurring outside of the time window, provide a pulse signal having an asserted value for a programmed period of time.