A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal on a PI stage output (PISO) node; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable to exhibit non-zero capacitances; and the PI stage including a first bank and a second bank corresponding outputs of which are coupled to PISO node; the first bank including parallel coupled tri-state (3S) inverters; the second bank including parallel coupled gated tri-state (G3S) inverters; each of the first and second banks being configured to receive a first clock signal; and the second bank being further configured to receive an output of the first bank, a multi-bit weighting signal and a second clock signal.