Analog-to-digital converter (ADC) circuitry including a delay domain ADC that outputs converted analog input data along with a delay domain clock. A clock delay driver outputs a digital domain clock, an early clock leading the digital domain clock signal, and a late clock lagging the digital domain clock. An output latch latches the ADC output by the digital domain clock signal. The circuitry includes a timing error detection circuit with inputs receiving the delay domain clock, the early clock, and the late clock. The timing error detection circuit outputs early and late fail flags responsive to detecting timing errors of the digital domain clock relative to the early and late clocks, respectively. Timing loop circuitry has an input coupled to the error flag output of the timing error detection circuitry, and an output coupled to a control input of the clock delay driver.

Analog-to-digital converter (ADC) circuitry including a delay domain ADC that outputs converted analog input data along with a delay domain clock. A clock delay driver outputs a digital domain clock, an early clock leading the digital domain clock signal, and a late clock lagging the digital domain clock. An output latch latches the ADC output by the digital domain clock signal. The circuitry includes a timing error detection circuit with inputs receiving the delay domain clock, the early clock, and the late clock. The timing error detection circuit outputs early and late fail flags responsive to detecting timing errors of the digital domain clock relative to the early and late clocks, respectively. Timing loop circuitry has an input coupled to the error flag output of the timing error detection circuitry, and an output coupled to a control input of the clock delay driver.

Analog-to-digital converter (ADC) circuitry including a delay domain ADC that outputs converted analog input data along with a delay domain clock. A clock delay driver outputs a digital domain clock, an early clock leading the digital domain clock signal, and a late clock lagging the digital domain clock. An output latch latches the ADC output by the digital domain clock signal. The circuitry includes a timing error detection circuit with inputs receiving the delay domain clock, the early clock, and the late clock. The timing error detection circuit outputs early and late fail flags responsive to detecting timing errors of the digital domain clock relative to the early and late clocks, respectively. Timing loop circuitry has an input coupled to the error flag output of the timing error detection circuitry, and an output coupled to a control input of the clock delay driver.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.