A semiconductor assembly includes a first FET having gate, source and drain terminals, a switching device being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal, a first gate lead, a second gate lead, a drain lead, and a source lead. The first and second gate leads, the drain lead, and the source lead form externally accessible terminals of the semiconductor assembly. A reverse blocking rating of the switching device is less than a reverse blocking rating of the first FET. A gate of the first FET is directly electrically connected to the first gate lead. A gate of the switching device is directly electrically connected to the second gate lead. The first FET and the switching device are the only active semiconductor devices connected between the first gate lead, the second gate lead, the drain lead, and the source lead.

A current limiter circuit for limiting current through a pass device is disclosed. The current limiter circuit includes a accurate/fast current limiter circuit, a coarse/slow current limiter control circuit and a pass device having an input port, an output port and an on/off control port. A control circuit couple to the accurate/fast current limiter circuit and the on/off control port is also included. The accurate/fast current limiter circuit is coupled to the input port and the output port and the coarse/slow current limiter control circuit is coupled to the input port and the output port and an on/off control port of the accurate/fast current limiter circuit.

The double pulse generator of the level shifter circuit takes out the rising edge and falling edge of the pulse width modulation signal PWM_H and generates corresponding narrow pulse signals. The two narrow pulse signals respectively pass through the pulse shaper to control the two field effect transistors in the switching circuit. The pulse width of the narrow pulse signal is not enough to completely switch on the two field effect transistors, so the generated waveform is a sawtooth wave; the drains of the two field effect transistors are respectively connected to the hysteresis-adjustable Schmidt trigger to restore the narrow pulse signal to the rising edge and falling edge pulse signal of the pulse width modulation signal PWM_HS with respect to the floating side VS, and then the signal is restored to the level-shifted pulse width modulation signal PWM HS after passing through the RS latch.

Embodiments of the present disclosure provide an apparatus and a method for generating a circuit clock signal. The apparatus comprises: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being respectively delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than that of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on a selection signal.

A semiconductor assembly includes a first FET having gate, source and drain terminals, a switching device being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal, a first gate lead, a second gate lead, a drain lead, and a source lead. The first and second gate leads, the drain lead, and the source lead form externally accessible terminals of the semiconductor assembly. A reverse blocking rating of the switching device is less than a reverse blocking rating of the first FET. A gate of the first FET is directly electrically connected to the first gate lead. A gate of the switching device is directly electrically connected to the second gate lead. The first FET and the switching device are the only active semiconductor devices connected between the first gate lead, the second gate lead, the drain lead, and the source lead.

A switching gate driver and method of operating the gate driver is described. The gate driver includes a first voltage source, and a clamping voltage source configured to have a voltage that is less than that of the first voltage source. There is also a current path, for initial charging of a gate voltage of the switching gate, between the first voltage source and a ground source; and a comparator which is configured to clamp the gate voltage to the clamping voltage source as it approaches the voltage of said clamping voltage source.

A clamp circuit includes a first MOS transistor and a second MOS transistor connected in series with the first MOS transistor. The first MOS transistor has a gate connected to a drain of the first MOS transistor. The second MOS transistor has a gate connected to a drain of the second MOS transistor. The clamp circuit is configured so that at least one of the first MOS transistor and the second MOS transistor causes a body effect.

A semiconductor assembly includes a first FET integrated within the semiconductor assembly and comprising gate, source and drain terminals. The semiconductor assembly further includes a low voltage switching device integrated within the semiconductor assembly and being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal.

A semiconductor device includes an input determination circuit. The input determination circuit includes: a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal; a reference voltage generation circuit that inputs a reference voltage that is generated from a connection point between a constant current source and a resistor to the reference voltage terminal of the comparator, the constant current source and the resistor being interposed between a second reference potential that is separated from the first reference potential and a third potential that is higher than the first reference potential and the second reference potential; and a first low pass filter that is interposed between a signal input system that is connected to the input voltage terminal of the comparator and the second reference potential.

A MOSFET active-disable switch is configured to clip an incoming signal in opposing directions when in an off state. By one approach the clipping is symmetrical and accordingly the switch clips both positive and negative peaks of the incoming signal. In many application settings it is useful for the clipping to serve to decrease a predetermined kind of resultant distortion such as even order distortion. In the on state this MOSFET active-disable switch is configured to not clip the incoming signal in opposing directions.