This disclosure provides systems, methods and apparatuses for processing analog signals with a wide dynamic range. In some implementations, the analog signal may be a current signal that is logarithmically scaled to decrease its dynamic range and converted to an output voltage using two or more diodes. A first diode may be used to scale a first range of the current signal and a second diode may be used to scale a second range of the current signal.

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage V.sub.GATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that V.sub.GATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V.sub.GATE; connecting to the gate of the power FET allows V.sub.GATE to be directly set.

According to a first aspect of the present inventive concept there is provided an equalizer system comprising a decision feedback equalizer (DFE), the DFE comprising: a static comparator configured as a decision device of the DFE; and a feedback path comprising a set of filter taps including at least a first filter tap; wherein the static comparator presents hysteresis and wherein a tap coefficient of the first filter tap is set such that an input signal level of the static comparator is shifted to compensate for the hysteresis.

A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

An SMPS current mode control loop with an adjusted cycle-by-cycle peak current limit for buck and boost (and bidirectional buck/boost) regulators. An SMPS regulator can include a PWM driver to drive switching control signals with a PWM duty cycle to an output terminal OUT, and a PWM controller to control the PWM duty cycle based on a current mode control loop that includes slope compensation to provide a signal VPK corresponding to a current sense signal from a current sense terminal CS, based on sensed peak current through the energy storage element, superimposed with an injected slope compensation current corresponding to a predefined slope compensation based on PWM duty cycle. Adjusted peak limit circuitry generates a signal VLMT corresponding to an adjusted peak current limit based on a pre-defined peak current limit threshold for the energy storage element, including generating a peak limit adjustment current corresponding to the injected slope compensation current, and combining the peak limit adjustment current with the pre-defined peak current limit threshold so that VLMT is substantially constant.

An encoder according to an embodiment of this disclosure includes a voltage generation circuit connected to a power supply through a diode and having a variable resistor, the voltage generation circuit outputting a voltage corresponding to a current flowing through the diode and a resistance value of the variable resistor, as a threshold value; a comparator for performing a comparison between an analog signal inputted from a detector for detecting rotation of a motor and the threshold value inputted from the voltage generation circuit, and outputting a comparison result as a comparator output; a resistance value variation circuit for varying the resistance value of the variable resistor; and a threshold value determination circuit for determining the threshold value based on a relationship between the resistance value and the comparator output.

A switching power converter is provided that uses at least two peak current thresholds. In particular, the switching power converter clamps a desired peak current to not fall below a low peak current threshold value while a rectified input voltage is decreasing and to not fall below a high peak current threshold value subsequent to zero crossing times for an AC input voltage.

A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.

A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.