A comparator may include: a first comparison unit suitable for generating a comparison voltage by performing a comparison operation between a pixel signal and a ramp signal; a time point detection unit suitable for detecting specific timing points of the comparison operation in response to the comparison voltage and a reference voltage, and generating a detection signal corresponding to the specific timing points; a period determination unit suitable for determining an additional supply period in response to the detection signal and a period determination control signal; and an additional current supply unit suitable for supplying an additional current to the first comparison unit during the additional supply period.

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage V.sub.GATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that V.sub.GATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V.sub.GATE; connecting to the gate of the power FET allows V.sub.GATE to be directly set.

A Light Emitting Diode, LED, driver arranged for driving at least one LED, said LED driver comprising a rectifier arranged for receiving an Alternating Current, AC, supply voltage and for providing an output Direct Current, DC, voltage to said at least one LED, a voltage regulating branch arranged for controlling an LED voltage provided to said at least one LED, via a supply line, wherein said voltage regulating branch is arranged for receiving said DC voltage from said rectifier, wherein said voltage regulating branch comprises, a capacitor arranged for providing said LED voltage to said at least one LED, a current limiter, connected in series with said capacitor, and arranged for charging said capacitor thereby providing said LED voltage and a feedback circuit arranged for controlling the charging of said capacitor by said current limiter, and thereby controlling the LED voltage provided to said at least one LED, by regulating a minimum residual headroom voltage present on a LED current limiter coupled in series with said at least one LED.

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage V.sub.GATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that V.sub.GATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V.sub.GATE; connecting to the gate of the power FET allows V.sub.GATE to be directly set.

Provided are a delay locked loop circuit and an operating method, for providing an output clock signal to a bidirectional data strobe (DQS). The delay locked loop circuit includes: a first delay line, configured to delay an input clock signal to generate the output clock signal; a second delay line, configured to receive the output clock signal and delay the output clock signal to generate a feedback clock signal; a phase comparator, configured to compare phases of the input clock signal and the feedback clock signal to adjust a delay of the first delay line; and a control circuit, controlling the second delay line, configured to adjust a delay of the second delay line to be aligned to a delay of an off-chip driver (OCD) coupled to the DQS.