A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Frequency synthesizer circuitry includes multi-phase clock generator circuitry, frequency divider circuitry, signal retiming circuitry, and signal combining circuitry. The multi-phase clock generator circuitry receives an input clock signal and generates a number of multi-phase clock signals. The frequency divider circuitry also receives the input clock signal and performs frequency division thereon to generate a reference signal. The signal retiming circuitry receives the reference signal and the multi-phase clock signals and generates a number of retiming signals. The signal combining circuitry combines two of the retiming signals to provide an output clock signal that has the same frequency as the reference signal but a different duty cycle.

A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.

An envelope tracking scheme can be used, such as to modulate a supply node of a power amplifier circuit to improve efficiency. For example, a magnitude or amplitude envelope of a signal to be modulated can be scaled and used to drive a node, such as a drain, of the power amplifier circuit. An envelope tracking signal can be generated such as having a bandwidth that is compressed as compared to a full-bandwidth envelope signal. A peak-value look ahead technique can be used, for example, so that amplitude compression or clipping of the transmit signal is suppressed when the bandwidth-compressed envelope tracking signal is used to modulate a supply node of the power amplifier used to amplify the transmit signal.

In accordance with an embodiment, a synchronous N pulse burst generator includes an input for an intermediate frequency trigger signal and a signal path extending from the input. The signal path includes a series of N AND gates and an OR gate. Each AND gate is arranged to receive two inputs from the signal path. The signal path introduces a time delay between the two inputs received by each AND gate. A second input of the two inputs is inverted. The signal path introduces the time delay between successive AND gates from the series of N AND gates. An OR gate receives outputs from the series of N AND gates and outputs an A/D clock signal.

A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signals separated in phase by a constructed amount of phase based on the specified mixing ratio. Additional apparatus, systems, and methods are disclosed.

A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.