The present invention provides a circuit having a plurality of modes, wherein the circuit includes a first circuit, a second circuit, a first multiplexer, a second multiplexer and a specific flip-flop. In the operations of the circuit, the first circuit is configured to generate a first signal, the second circuit is configured to generate a second signal, the first multiplexer is configured to output one of the first signal and the second signal according to a mode selection signal, the second multiplexer is configured to output one of a first clock signal and a second clock signal according to the mode selection signal, and the specific flip-flop is configured to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

An example gate driver for an array of sensing pixels is disclosed. The gate driver includes a first flip-flop including a first data input and a first data output. The first data output is coupled to a first group of sensing pixels of the array. The gate driver also includes a second flip-flop including a second data input and a second data output. The second data output is coupled to a second group of sensing pixels of the array. The gate driver further includes a first insertion circuit configured to receive a first start signal and to cause, based on the first start signal, the second flip-flop to drive the second group of sensing pixels without the first flip-flop driving the first group of sensing pixels for a scan of the array.

A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.

A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.

In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.