An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

A system for controlling a hold-margin in a semiconductor memory device includes a programmable RC network communicatively coupled to a delay logic circuit, a latch clock generator and a latch circuit. A delay associated with a clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the delay logic circuit and at least one of the load cell and a wire routed across at least one of a column and a row of the semiconductor memory device. The system controls the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.

According to an embodiment, a semiconductor device may be provided. The semiconductor device may include an internal clock generation circuit configured to generate a plurality of internal clock signals respectively from a plurality of division clock signals. The semiconductor device may include a data input and output (I/O) circuit configured to output input data as output data in synchronization with the plurality of internal clock signals. Each bit of the output data may be outputted in sequential order in synchronization with an internal clock signal from the plurality of internal clock signals.

An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

According to an embodiment, a semiconductor device may be provided. The semiconductor device may include an internal clock generation circuit configured to generate a plurality of internal clock signals respectively from a plurality of division clock signals. The semiconductor device may include a data input and output (I/O) circuit configured to output input data as output data in synchronization with the plurality of internal clock signals. Each bit of the output data may be outputted in sequential order in synchronization with an internal clock signal from the plurality of internal clock signals.

Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.