An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

A comparator includes: a first selector for selecting one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel; a first comparator for comparing the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit for determining an output voltage at the current time of the target channel, based on the comparison result of the first comparator.

An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.

A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.

A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.

A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.

A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.

A comparator circuit's signal range can be enhanced using an input signal attenuation circuit. In an example, a comparator circuit receives an input signal and a reference signal. The input signal can be conditioned by one or both of the attenuation circuit and a conditioning circuit, and a resulting conditioned signal can be presented to a compare element. Under first operating conditions where the input signal is approximately equal to the reference signal, the attenuation circuit can be substantially bypassed and a first resulting conditioned signal can be presented to the compare element. Under second operating conditions where the input signal is substantially greater than the reference signal, the attenuation circuit receives a portion of the input signal and a different second resulting conditioned signal can be presented to the compare element.