A switching power converter with good stability and transient response is presented. There is provided a controller for a switching power converter of the type comprising one or more power switches. The controller contains a pulse width modulation comparator arranged to output a digital control signal to control the power switches of the switching power converter. A first input of the pulse width modulation comparator is derived from an output voltage of the switching power converter via a first feedback path. A second input of the pulse width modulation comparator is derived from the output voltage of the switching power converter via a second feedback path. One of the feedback paths has a signal extractor and a differential amplifier arranged to filter the output voltage and to provide good ground noise rejection.

A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.

A comparator includes a comparison circuit and a positive feedback circuit. The comparison circuit generates a comparison signal by comparing an input signal and a reference signal. The positive feedback circuit generates an output signal based on the comparison signal, such that the output signal transitions more rapidly than the comparison signal. The positive feedback circuit includes a first circuit configured to electrically connect a first power supply voltage to a conversion node in response to a transition of the comparison signal and electrically disconnect the first power supply voltage from the conversion node in response to a transition of the output signal, a second circuit configured to electrically connect a second power supply voltage to the conversion node in response to the transition of the output signal, and an output circuit configured to generate the output signal based on a voltage of the conversion node.

The present disclosure is applicable to electronic fields, and provides a voltage comparator. The voltage comparator includes a first branch, a second branch and a third branch. The first branch and the second branch both have self-biasing capabilities, and require no dedicated bias circuit. Under the same power voltage, the static power consumption of the voltage comparator is relatively low; fewer the power consuming branches exist in the circuit, and the reliability is high under low power consumption.

A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

A comparator circuit having an offset voltage includes a first input circuit, a second input circuit and a control circuit. The first input circuit includes a first input terminal receiving a first input signal. The second input circuit includes a second input terminal receiving a second input signal. The control circuit is coupled to a first intermediate terminal and a second intermediate terminal and resets a voltage at the first intermediate terminal and a voltage at the second intermediate terminal according to an offset cancellation voltage. The first intermediate terminal is coupled between the first input terminal and a first output terminal of the comparator circuit, the second intermediate terminal is coupled between the second input terminal and a second output terminal of the comparator circuit, and the first intermediate terminal and the second intermediate terminal are symmetric terminals in the comparator circuit.

Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

A squelch detector, including: an input configured to receive an input signal; a peak detector connected to the input configured to detect a maximum value of the input signal wherein the peak detector includes a refresh input configured to receive a refresh signal to refresh the output of the peak detector, a valley detector connected to the input configured to detect a minimum value of the input signal wherein the valley detector includes a refresh input configured to receive the refresh signal to refresh the output of the valley detector, and a comparator including a first signal input connected to an output of the peak detector, a second input connected to an output of the valley detector, and a first reference input, wherein the comparator is configured to compare a difference between an output of the peak detector and an output of the valley detector and a reference value received at the first reference input and configured to produce an output based upon the comparison.

The present technology relates to an AD conversion device, an AD conversion method, an image sensor, and an electronic apparatus that are able to achieve high-speed, low-power-consumption AD conversion. In a case where an electrical signal and a variable-level reference signal are compared by a comparator and the result of comparison is used to perform AD (Analog to Digital) conversion of the electrical signal, control is exercised in such a manner that a bias current flowing in the comparator to operate the comparator during a certain section of the reference signal including a section where the reference signal changes is increased from a first current, which is larger than 0 (zero), to a second current, which is larger than the first current. The present technology is applicable, for example, to AD conversion of an electrical signal.

A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.