A comparator circuit is described, which is configured to provide a control current and a control voltage based on a first input voltage and a second input voltage. The comparator circuit comprises an input amplifier configured to generate an output signal based on the first input voltage and the second input voltage, and offset means configured to generate a first offset. Furthermore, the comparator circuit comprises a first output circuit configured to generate the control current based on the output signal and based on the first offset. In addition, the comparator circuit comprises a second output circuit configured to generate the control voltage based on the output signal and not based on the first offset.

The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator.

The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.

A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. The input is coupled to the control terminal of at least one transistor of the first pair. The amplitude detector includes a first node providing a voltage indicative of the amplitude voltage. The first node is in series with each of the first pair of transistors. The circuit includes a compensation circuit. The compensation circuit includes a second pair of transistors configured in parallel and a second node. The second node is coupled in series with each transistor of the second pair. The circuit includes an amplifier including a first amplifier input coupled to the first node and a second amplifier input coupled to the second node.

A comparison circuit includes a comparator having a first input terminal receiving a first input voltage through a first capacitor, and a second input terminal receiving a second input voltage through a second capacitor, and an output terminal. A first switch has one end connected to the first input terminal and is turned on in a sample phase to set a voltage of the first input terminal as a voltage of the output terminal. A second switch has one end connected to the second input terminal and is turned on in the sample phase to set a voltage of the second input terminal as a reference voltage. A third switch is turned on in a comparison phase to equalize voltages of the other end of the first switch and the other end of the second switch.

This document discusses, among other things, a voltage comparator, an integrated circuit, or a voltage comparison method having increased precision. The hysteresis comparator or the integrated circuit can include first and second input transistors, each having a gate configured to receive a respective first or second input voltage. A bias power source can generate a bias current to a first node by applying a voltage through a first resistor. The first node can be connected to a source of the first input transistor through a second resistor and to a source of the second input transistor through a third resistor. The first, second, and third resistors can include the same type of resistor, with the second and third resistors having different resistance values.

There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.

An apparatus is provided which comprises: a bi-directional switch; and a comparator coupled to the bi-directional switch, the comparator having: a first input coupled to a first terminal of the bi-directional switch; a second input coupled to a second terminal of the bi-directional switch; and an output coupled to a body or substrate of the bi-directional switch.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

Solid-state image capturing elements are disclosed. In one example, a solid-state image capturing element includes a noise-cancelling-signal generating circuit connected to a pixel power source. It executes a gain change and a polarity inversion on a first noise cancelling signal to output a second noise cancelling signal. The element also includes a DA converter that outputs a reference signal and converts a current of the second noise cancelling signal into a voltage to superpose the converted voltage on the reference signal; a comparator that receives inputs of the reference signal and a pixel signal and outputs an inversion signal according to the pixel signal and a gain setting; a counter that converts an inversion timing of the comparator into a digital value; and a gain controlling unit that outputs, when changing a gradient of the reference signal and an input capacity to execute a gain control on the comparator.