The present invention provides a dynamic comparator including a dynamic amplifier and a latch circuit. The dynamic amplifier includes a first input pair, a current source and a gain boosting circuit. The first input pair is configured to receive an input signal to generate an amplified signal at an output terminal. The current source is coupled between the first input pair and a first reference voltage. The gain-boosting circuit is coupled between the first input pair and a second reference voltage, and is configured to receive the input signal to selectively inject current to the output terminal or sink current from the output terminal. The latch circuit is coupled to the dynamic amplifier, and is configured to receive the amplified signal to generate an output signal.

A comparator includes a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit. The first-stage circuit includes a first input circuit and a second input circuit. The first switching circuit is configured to control the conduction of the first input circuit, and the second switching circuit is configured to control the conduction of the second input circuit. The first input circuit is configured to generate a first differential signal in a sampling phase when being switched on. The second input circuit is configured to generate a second differential signal in a sampling phase when being switched on. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.

An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

A memory device and a slew rate detector are provided. The slew rate detector includes a clock signal generator, a pulse signal generator, a plurality of sampling comparators, and a detection result generator. The clock signal generator multiplies a frequency of a base clock signal to generate clock signals. The pulse signal generator generates first pulse signals and second pulse signals according to the clock signals. Each of the sampling comparators samples each of transmission signals to generate a reference signal according to the first pulse signals, and samples each of the transmission signals to generate a comparison signal according to the second pulse signals. The sampling comparators compare the reference signals with the comparison signals to generate comparison results. The detection result generator performs an operation on the comparison results to generate detection results.

A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

A comparator circuit has a pre-charging and early reset output stage. The comparator circuit includes: a first pre-charging transistor and a second pre-charging transistor. A gate of the first pre-charging transistor is connected to a pre-charging signal, and a gate of the second pre-charging transistor is connected to a main clock signal, wherein the pre-charging signal is enabled earlier than the main clock signal. At a pre-charging phase, there is a small electric current, and a comparator slowly amplifies an input small signal to reduce noise; and the electric current is increased after a certain time delay, such that on the basis of pre-charging, the comparator rapidly completes a pre-amplification phase and then enters a regeneration phase.

A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

A comparator circuit has a pre-charging and early reset output stage. The comparator circuit includes: a first pre-charging transistor and a second pre-charging transistor. A gate of the first pre-charging transistor is connected to a pre-charging signal, and a gate of the second pre-charging transistor is connected to a main clock signal, wherein the pre-charging signal is enabled earlier than the main clock signal. At a pre-charging phase, there is a small electric current, and a comparator slowly amplifies an input small signal to reduce noise; and the electric current is increased after a certain time delay, such that on the basis of pre-charging, the comparator rapidly completes a pre-amplification phase and then enters a regeneration phase.

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.