A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

A system includes a switching converter with an output inductor. The switching converter also includes a switch set with a switch node coupled to the output inductor. The switching converter also includes a first drive stage coupled to the switch set. The switching converter also includes a second drive stage coupled to the switch set. The switching converter also includes a controller coupled to the first drive stage and the second drive stage. The controller includes a supply voltage detector circuit. The controller also includes a level shifter coupled to an output of the supply voltage detector circuit. The controller also includes a selection circuit coupled between the level shifter and the second drive stage.

A drive device driving a power converter that includes a switching element formed from a wide bandgap semiconductor, includes a PWM-signal output unit that generates a drive signal that drives the switching element with PWM; an on-speed reducing unit that, when the switching element is changed from off to on, reduces a change rate of the drive signal; and an off-speed improving unit that, when the switching element is changed from on to off, draws charge from the switching element at a high speed and with a charge drawing performance higher than that at a time when the switching element is changed from off to on.

An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.

A switch device includes a first radio-frequency (RF) terminal, a second RF terminal, a first transistor, a second transistor, and a variable resistance element. The first transistor includes a first terminal coupled to the first RF terminal, a second terminal, and a control terminal coupled to a control signal terminal providing a control signal. The second transistor includes a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the second RF terminal, and a control terminal. The variable resistance element is coupled between the second terminal of the first transistor and a bias voltage terminal. When the first transistor and the second transistor are in a transient state, the variable resistance element provides a lower resistance. When the first transistor and the second transistor are in an ON state, the variable resistance element provides a higher resistance.

A method of controlling a power converter, including executing a plurality of cycles, including: turning on a first switch during a first period, the first switch coupled to a power supply and a switch node; turning on a second switch during a second period, the second switch coupled to the switch node; turning on a third switch at a first time during the second period and turning the third switch off at a second time after the second period by a first open signal including a high discharge signal followed by a lower discharge signal, the third switch coupled to an auxiliary node and to a second inductor coupled to the auxiliary node; and turning on a fourth switch at a third time after the second time and turning the fourth switch off during the first period of a succeeding cycle, the fourth switch coupled to the auxiliary node.

In a drive circuit, a rate adjuster adjusts a charging speed of a MOSFET to be faster than the charging speed of an IGBT when a drive state changer changes the first switching element from the off state to the on state first, and changes the second switching element from the off state to the on state next. The rate adjuster also adjusts a discharging speed of the MOSFET to be faster than the discharging speed of the IGBT when the drive state changer changes the MOSFET from the on state to the off state first, and changes the IGBT from the on state to the off state next.

A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.

A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.

Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.