Circuitry for controlling current between a load and a power supply, the circuitry comprising: an output stage comprising: an input node configured to be coupled to the power supply; and an output node configured to be coupled to the load; and one or more control nodes for controlling a conduction path between the input node and the output node; and protection circuitry coupled to the one or more control nodes, the protection circuitry configured to break the conduction path between the input node and the output node when a load voltage at the output node exceeds a supply voltage at the input node, wherein the protection circuitry comprises: an active protection circuit configured to break the conduction path when the supply voltage exceeds an operational threshold of the active protection circuit; and a passive protection circuit configured to break the conduction path when the supply voltage is below an operation threshold of the active protection circuit.

A semiconductor device includes a first external electrode with a first electrode surface portion; a second external electrode with a second electrode surface portion; a MOSFET chip with a built-in Zener diode which includes an active region and a peripheral region; a control IC chip which drives the MOSFET chip based on voltage or current between a drain electrode and a source electrode of the MOSFET chip; and a capacitor which supplies power to the MOSFET chip and the control IC chip. The first electrode surface portion is connected to either the drain electrode or the source, the second electrode surface portion is connected to either the source electrode or the drain electrode, a plurality of unit cells of the MOSFET with the built-in Zener diode are provided in the active region, and the breakdown voltage of the Zener diode is set to be lower than that of the peripheral region.

Unique systems, methods, techniques and apparatuses of solid state circuit breaker protection are disclosed. One exemplary embodiment is a solid state circuit breaker comprising a primary switching device including a first terminal and a second terminal and a voltage clamping circuit coupled in parallel with the primary switching device. The voltage clamping circuit includes a metal-oxide varistor (MOV) coupled in series between the first terminal and an auxiliary semiconductor device, the auxiliary semiconductor device being arranged so as to selectively couple the MOV with the second terminal, and a bypass circuit coupled between the first terminal and the auxiliary semiconductor device.

A snubber circuit configured to be coupled to a switching circuit, comprises a snubber capacitor; a diode; and a coil, wherein the switching circuit includes an upper switch element coupled between a high potential node and a switch node, a lower switch element coupled between the switch node and a reference potential node, and a bypass capacitor coupled between the high potential node and the reference potential node, a positive electrode of the snubber capacitor is configured to be coupled to the high potential node, an anode of the diode is coupled to a negative electrode of the snubber capacitor, and a cathode of the diode is coupled to the switch node, and one end of the coil is coupled to the negative electrode of the snubber capacitor, and another end of the coil is coupled to the reference potential node.

An output stage circuit includes a first operational amplifier, a second operational amplifier, a switch circuit, a clamp circuit and at least one pull-low transistor. The first operational amplifier is operated in a first voltage domain. The second operational amplifier is operated in a second voltage domain. The switch circuit is coupled to the first operational amplifier and the second operational amplifier. The clamp circuit is coupled between the switch circuit and a plurality of output terminals of the output stage circuit. The at least one pull-low transistor is coupled to the switch circuit.

A drive circuit for a switch drives an upper-arm switch and a lower-arm switch that include body diodes. Of the body diodes in upper- and lower-arm switches, the diode through which a feedback current flows during a dead time is a target diode. Of the upper- and lower-arm switches, the switch that includes the target diode is a target switch. The remaining switch is an opposing arm switch. The drive circuit maintains an electric potential of a control terminal relative to a second terminal of the target switch at a negative voltage over a period from a timing subsequent to a start timing of a dead time immediately after the target switch is switched to an off-state until a point within a period over which the opposing arm switch is set to an on-state, and subsequently maintains the electric potential at an off-voltage until a next dead time is ended.

A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

The present disclosure concerns a current limiting circuit for a power converter, which may be used to limit charge and discharge currents for electrical power storage units. In an example embodiment, a current limiting circuit comprises: first and second field effect transistors, each having source, gate and drain connections, wherein the source connection of the first transistor is connected to the gate connection of the second transistor and the source connection of the second transistor is connected to the gate connection of the first transistor; and a resistor connected between the source connections of the first and second transistors, wherein drain connections of the first and second transistors are connectable between a DC electrical power supply and an electrical load for limiting a maximum current flowing between the electrical power supply and the electrical load.

A driver circuit is provided. The driver circuit comprises a power transistor and a gate driver circuit arrangement. The driver circuit is integrated in a package. In addition, the driver circuit comprises a terminal for an external transistor. The external transistor and the power transistor are controlled by the gate driver circuit arrangement in a mutually corresponding manner.

The present disclosure discloses an output circuit having a voltage-withstanding mechanism that includes a PMOS, a NMOS, a voltage-withstanding auxiliary NMOS and a voltage-withstanding auxiliary circuit. The PMOS includes a first source terminal and a first drain terminal coupled to a voltage source and an output terminal and a first gate receiving a first input signal. The NMOS includes a second source terminal and a second drain terminal coupled to a ground terminal and a connection terminal and a second gate receiving a second input signal. The auxiliary NMOS includes a third drain terminal and a third source terminal coupled to the output terminal and the connection terminal The auxiliary circuit is coupled to the voltage source and a third gate of the auxiliary NMOS and provides a current conducting mechanism and a resistive mechanism respectively when the output terminal is operated at a logic high level and a logic low level.