An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

A driver circuit is provided. The driver circuit comprises a power transistor and a gate driver circuit arrangement. The driver circuit is integrated in a package. In addition, the driver circuit comprises a terminal for an external transistor. The external transistor and the power transistor are controlled by the gate driver circuit arrangement in a mutually corresponding manner.

A motor protecting circuit is provided. A first terminal of each of high-side transistors is coupled to a power supply voltage. A second terminal of each of low-side transistors is grounded. Second terminals of the high-side transistors are respectively connected to first terminals of the low-side transistors. An overvoltage detector circuit is coupled to the power supply voltage of an output circuit. When the overvoltage detector circuit determines that the power supply voltage of the output circuit is higher than a voltage threshold, the overvoltage detector circuit outputs an overvoltage detected signal to a controller circuit. According to the overvoltage detected signal, the controller circuit controls a driver circuit to turn on at least one of the high-side transistors and at least one of the low-side transistors at the same time.

An electronic module includes a power supply wiring line disposed on a substrate along a first side and connected to a power supply terminal, a ground wiring line disposed on the substrate along a second side and connected to a ground terminal, and first to third half bridges each having a high-side switch and a low-side switch connected in series between the power supply wiring line and the ground wiring line. Connection points of the high-side switches and the low-side switches are connected to first to third motor terminals and also connected in parallel to one another. The first motor terminal, the second motor terminal, and the third motor terminal are disposed between the power supply terminal and the ground terminal.

A linear power supply circuit includes: an output stage including a first output transistor and a second output transistor, which are provided between an input terminal to which an input voltage is able to be applied and an output terminal to which an output voltage is able to be applied and are connected in parallel to each other; a driver configured to drive the first output transistor and the second output transistor based on a difference between a voltage based on the output voltage and a reference voltage; a resistor inserted between a gate of the first output transistor and a gate of the second output transistor; a capacitor having one end connected to the input terminal and the other end connected to a connection node between the resistor and the gate of the second output transistor; and a clamp element connected in parallel to the resistor.

A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. One or more non-dissipative elements may be connected between the common node of the first pair of switches and the common node of the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. In one sequence, switches in a selected driver cell may subtract a specified voltage from an input voltage, bypass the selected driver cell, and add the specified voltage to the input voltage.

A motor protecting circuit is provided. A first terminal of each of high-side transistors is coupled to a power supply voltage. A second terminal of each of low-side transistors is grounded. Second terminals of the high-side transistors are respectively connected to first terminals of the low-side transistors. An overvoltage detector circuit is coupled to the power supply voltage of an output circuit. When the overvoltage detector circuit determines that the power supply voltage of the output circuit is higher than a voltage threshold, the overvoltage detector circuit outputs an overvoltage detected signal to a controller circuit. According to the overvoltage detected signal, the controller circuit controls a driver circuit to turn on at least one of the high-side transistors and at least one of the low-side transistors at the same time.

An electromagnetic interference regulator by use of capacitive parameters of the field-effect transistor for detecting the induced voltage and the induced current of the field-effect transistor to determine whether the operating frequency of the field-effect transistor is within the preset special management frequency of electromagnetic interference. When the basic frequency and the multiplied frequency exceed the limit, the content of the external capacitor unit can be adjusted to assist the products using field-effect transistors to maintain excellent electromagnetic interference adjustment capabilities under various loads, thereby optimizing the characteristics of electromagnetic interference.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A snubber circuit includes a snubber substrate including an electrically insulating carrier and an electrically conducting structured layer applied thereon, the electrically conducting structured layer including two segments. The snubber circuit further includes two electrically resistive layers, each resistive layer being applied onto the two segments of the electrically conducting structured layer of the snubber substrate, and a capacitor disposed on the electrically resistive layers and having two terminals, each terminal being electrically connected to one of the electrically resistive layers. Further, a power semiconductor module having such a snubber circuit is disclosed.