A circuit device and a method for safely disconnecting a semiconductor switching element, in particular a MOSFET, are provided, wherein the semiconductor switching element comprises a gate terminal, a source terminal and a drain terminal, wherein, during operation of the semiconductor switching element, a current path between the drain terminal and the source terminal can be reversibly disconnected by the gate terminal, and the gate terminal comprises a gate voltage potential and the source terminal comprises a source voltage potential. A fuse unit is arranged between the gate terminal and the source terminal, which fuse unit is set up and designed, as a function of a potential difference between the gate voltage potential and the source voltage potential, so as to electrically connect the gate terminal to the source terminal after the current path is disconnected, so that the gate voltage potential and the source voltage potential are adapted.

A circuit device and a method for safely disconnecting a semiconductor switching element, in particular a MOSFET, are provided, wherein the semiconductor switching element comprises a gate terminal, a source terminal and a drain terminal, wherein, during operation of the semiconductor switching element, a current path between the drain terminal and the source terminal can be reversibly disconnected by the gate terminal, and the gate terminal comprises a gate voltage potential and the source terminal comprises a source voltage potential. A fuse unit is arranged between the gate terminal and the source terminal, which fuse unit is set up and designed, as a function of a potential difference between the gate voltage potential and the source voltage potential, so as to electrically connect the gate terminal to the source terminal after the current path is disconnected, so that the gate voltage potential and the source voltage potential are adapted.

A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.

A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

A circuit device and a method for safely disconnecting a semiconductor switching element, in particular a MOSFET, are provided, wherein the semiconductor switching element comprises a gate terminal, a source terminal and a drain terminal, wherein, during operation of the semiconductor switching element, a current path between the drain terminal and the source terminal can be reversibly disconnected by the gate terminal, and the gate terminal comprises a gate voltage potential and the source terminal comprises a source voltage potential. A fuse unit is arranged between the gate terminal and the source terminal, which fuse unit is set up and designed, as a function of a potential difference between the gate voltage potential and the source voltage potential, so as to electrically connect the gate terminal to the source terminal after the current path is disconnected, so that the gate voltage potential and the source voltage potential are adapted.

A circuit device and a method for safely disconnecting a semiconductor switching element, in particular a MOSFET, are provided, wherein the semiconductor switching element comprises a gate terminal, a source terminal and a drain terminal, wherein, during operation of the semiconductor switching element, a current path between the drain terminal and the source terminal can be reversibly disconnected by the gate terminal, and the gate terminal comprises a gate voltage potential and the source terminal comprises a source voltage potential. A fuse unit is arranged between the gate terminal and the source terminal, which fuse unit is set up and designed, as a function of a potential difference between the gate voltage potential and the source voltage potential, so as to electrically connect the gate terminal to the source terminal after the current path is disconnected, so that the gate voltage potential and the source voltage potential are adapted.

A gate driver circuit drives a switching transistor. A variable current source generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount. A current distribution circuit is configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero. A first transistor fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor. A second transistor fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor.

A switching assembly for transferring trains of pulses, including a first terminal and a second terminal. A first plurality of first relays is connected in parallel, and have first contacts connected to the first assembly terminal, and second contacts. A first capacitor is connected in parallel with the first relays. A second plurality of second relays is connected in parallel, and have third contacts, and fourth contacts connected to the second assembly terminal. A second capacitor is connected in parallel with the second relays. A connection connects the second contacts to the third contacts. The pulses have amplitudes of at least 2 kilovolts. On activation of the first and second relays the first and second contacts connect and the third and fourth contacts connect, so that the first and second assembly terminals connect. On deactivation of the first and second relays the first and second assembly terminals disconnect.