Systems, methods, and apparatuses are provided for a single or multi-dimmer system having improved reliable connectivity between a dimmer assembly and a switch or between two or more dimmer assemblies.

A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn closer to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn closer to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.

A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.

A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.

A single-pole double-throw switch includes switching units which are set between a first port and a second port and between the first port and a third port, respectively, and are configured to perform complementarily. The each switching unit includes an antenna port, a circuit port, a transmission line configured to couple them, and a switching element connected between the transmission line and a ground. The switching element includes a parallel circuit including a transistor and an inductor connected in parallel, and a capacitor connected in series with the parallel circuit. The transmission line has a characteristic impedance different from a impedance seen inside the switching unit from the antenna port and a impedance seen inside the switching unit from the circuit port.