A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Linearity of a PAM-4 voltage-mode driver is improved using current compensation. The driver receives a first input data signal having a first logic level and a second input data signal having a second logic level. In an additive current mode, when the first logic level matches the second logic level, the driver uses switch circuitry to form an auxiliary current path through which supplementary current (I_Supplementary) flows from a voltage regulator. In a primary current mode, when the first logic level does not match the second logic level, the driver uses the switch circuitry to break the auxiliary current path, thereby preventing the supplementary current (I_Supplementary) from flowing from the voltage regulator.

An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (I.sub.EE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (R.sub.EA1, R.sub.EA2, R.sub.EA3, R.sub.EA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of R.sub.EA.Math.I.sub.EEthe amplitude of an input analog signal is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (I.sub.EE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (R.sub.EA1, R.sub.EA2, R.sub.EA3, R.sub.EA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of R.sub.EA.Math.I.sub.EEthe amplitude of an input analog signal is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

A two-stage high-power RF limiter circuit for an RF signal receiver incorporates a heavy limiting stage to limit high energy pulses of a received RF signal to a desired power threshold over a sustained time period, while a light limiting stage reacts quickly to high energy pulses to reduce spike leakage associated with the slower reaction time of the heavy limiting stage. Both heavy and light limiting stages incorporate PIN diodes biased to a voltage just below the desired power threshold (the light limiter biased to a slightly higher voltage than the heavy limiter) so the PIN diodes do not activate until power levels are high enough to warrant limiting. The holdoff voltage across the PIN diodes is maintained by Zener diodes biased to a voltage corresponding to the power threshold, allowing the PIN diodes to self-bias once the power threshold is reached.

A front-end circuit includes a first filter on a path connecting a common terminal and a first input/output terminal, a second filter on a path connecting the common terminal and a second input/output terminal, and a first switch on the path connecting the common terminal and the first input/output terminal. The first switch receives at least one of a first control signal and a second control signal. The first control signal increases a difference between a first voltage applied to the first switch to turn the first switch to a non-conductive state and a threshold voltage determining whether or not the first switch is turned to a conductive state. The second control signal increases a difference between a second voltage applied to the first switch to turn the first switch to the conductive state and the threshold voltage.

A front-end circuit includes a first filter on a path connecting a common terminal and a first input/output terminal, a second filter on a path connecting the common terminal and a second input/output terminal, and a first switch on the path connecting the common terminal and the first input/output terminal. The first switch receives at least one of a first control signal and a second control signal. The first control signal increases a difference between a first voltage applied to the first switch to turn the first switch to a non-conductive state and a threshold voltage determining whether or not the first switch is turned to a conductive state. The second control signal increases a difference between a second voltage applied to the first switch to turn the first switch to the conductive state and the threshold voltage.

An RF switch for connecting an antenna to a transceiver is described. The RF switch includes a first switchable capacitor arranged between a first terminal and a common terminal and a second switchable capacitor arranged between a second terminal and the common terminal. Each of the first and second switchable capacitors are switchable between a pass state and a blocking state. The capacitance value in the pass state is higher than the capacitance value in the blocking state.