An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Voltage monitoring is used to address the issue of output overload and pre-charging of coupling capacitors are described as solutions to uncontrolled pre-charging of coupling capacitors. Pre-charging of coupling capacitors are implemented using current sources.

Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Methods and devices based on monitoring coupling capacitors voltages and pre-charging such coupling capacitors using current sources are also described. The current sources can be implemented using negative voltages provided by negative voltage sources such as charge pumps.

An integrated circuit may include a power transistor coupled between a supply pin and an output pin; a current sensing circuit configured to sense a load current passing through the power transistor and to provide a respective current sense signal; a first configuration pin; a current output circuit configured to provide a diagnosis current at a current output pin; a diagnosis pin for receiving a diagnosis request signal; and a control circuit configured to: select a characteristic curve representing a current versus time characteristic dependent on a external circuit connected to the first configuration pin; generate a drive signal for the power transistor dependent on the selected characteristic curve and the current sense signal; and controldependent on a pulse pattern of the diagnosis request signalthe current output circuit to set the value of the diagnosis current such that it represents the load current or the selected characteristic curve.

An integrated circuit is described herein. In accordance with one embodiment the circuit includes a transistor coupled between a supply pin and an output pin, a current output circuit configured to provide a diagnosis current at an current output pin, a current sensing circuit coupled to the transistor and configured to generate a first current sense signal indicative of a load current passing through the transistor and a second current sense signal indicative of the load current. The current output circuit is configured to select, dependent on a control signal, one of the following as diagnosis current: the first current sense signal and the second current sense signal.

A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.

The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.

In one embodiment, an impedance matching network includes an electronically variable reactance element (EVRE) comprising discrete reactance elements and corresponding switches. The switches are configured to switch in and out the discrete reactance elements to alter a total reactance provided by the EVRE. A monitoring circuit is operably coupled to the EVRE. For each discrete reactance element, the monitoring circuit monitors a value related to the discrete reactance element or its corresponding switch. Upon determining the monitored value exceeds a predetermined amount, the monitoring circuit the discrete reactance element of the EVRE from switching in or out.

Circuits and devices are provided for reliably holding a normally-off Gallium Nitride (GaN) power transistor, such as a Gate Injection Transistor (GIT), in a non-conducting state when a gate of the power transistor is not driven with an active (turn-on) control signal. This is accomplished by coupling a normally-on pulldown transistor between the gate and the source of the power transistor, such that the pulldown transistor shorts the gate to the source when the power transistor is not set for its conducting state. The pulldown transistor is preferably located on the same semiconductor die as, and in close proximity to, the power transistor, so as to avoid spurious noise at the power transistor gate that may unintentionally turn on the power transistor. A pulldown control circuit is coupled to the gate of the pulldown transistor and autonomously turns off the pulldown transistor when the power transistor is set to conduct.

A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.