A method of controlling a half-bridge circuit includes receiving an analog feedback signal proportional to an output of the half-bridge circuit, comparing the received analog feedback signal with a threshold value, selecting a digital feedback signal based on a result of the comparing, comparing the digital feedback signal with a digital reference signal to generate a digital error signal, integrating the digital error signal to generate an integration error signal, downscaling the integral error signal to generate a downscaled integration signal, sampling the downscaled integration signal to generate a sampled integration signal, and generating pulsed signals from the sampled integration signal to provide an input to the half-bridge circuit.

A device is provided that includes a power transistor and an overcurrent detection logic. The overcurrent detection logic has a first stable state providing a first signal level on a status output terminal and a second stable state providing a second signal level on the status output terminal. The overcurrent detection logic changes from the first stable state to the second stable state in response to detecting that a current through the power transistor exceeds a current limit. The overcurrent detection logic remains in the second state when the current through the transistor drops below the limit after exceeding the current limit.

A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

A high-voltage output driver (1) for a sensor device (100) with reverse current blocking comprises a supply node (SN) to apply a supply voltage (VHV) and an output node (OP) to provide an output signal (OS) of the high-voltage output driver (1). The high-voltage output driver (1) comprises a driver transistor (MP0) being disposed between the supply node (SN) and the output node (OP). The high-voltage output driver (1) further comprises a bulk control circuit (20) to apply a bulk control voltage (Vwell) to a bulk node (BMP0) of the driver transistor (MP0), and a gate control circuit (30) to apply a gate control voltage (GCV) to the gate node (GMP0) of the driver transistor (MP0).

A system may include a power source. The power source supplies a first voltage. The system may also include a voltage regulator that receives the first voltage and supply a second voltage. Additionally, the system may include a microcontroller that receives the second voltage and output the second voltage via an output pin. Further, the system may include a switching element that receives the second voltage from the output pin of the controller at a first terminal and receives the first voltage from the power supply at a second terminal. The switching element selectively charges a first capacitor based on a difference between the first voltage and the second voltage.

An integrated circuit that may be employed as a smart switch is described herein. The integrated circuit may include a first power transistor coupled between a supply pin and a first output pin and a second power transistor coupled between the supply pin and a second output pin. The first and the second power transistors each having an intrinsic body diode which allows reverse conduction. The integrated circuit further includes a control circuit that is configured to trigger a switch-on and switch-off of the first and the second power transistors based on a first input signal and a second input signal, respectively. Furthermore, the integrated circuit includes a protection circuit configured to detect, for the first and the second power transistors, a transition from a reverse conducting state into a forward conducting state, and vice versa, and to generate an error signal in response to certain detections.

A system may include a power source. The power source supplies a first voltage. The system may also include a voltage regulator that receives the first voltage and supply a second voltage. Additionally, the system may include a microcontroller that receives the second voltage and output the second voltage via an output pin. Further, the system may include a switching element that receives the second voltage from the output pin of the controller at a first terminal and receives the first voltage from the power supply at a second terminal. The switching element selectively charges a first capacitor based on a difference between the first voltage and the second voltage.

A device includes a first switch and a first diode connected in parallel between a midpoint and a first terminal of the hybrid power device, a second switch and a second diode connected in parallel between the midpoint and a second terminal of the hybrid power device, a third switch coupled between the first terminal and the second terminal, and a third diode connected between the first terminal and the second terminal.

A driver circuit for switching edge modulation of a power switch. The driver circuit includes a first driver circuit input including a downstream input node, and a power switch including an upstream first gate node. A charging path including a charging resistor is situated between the input node and the first gate node. A discharging path including a discharging resistor is situated between the input node and the first gate node. A gate path is situated between the input node and the first gate node. A power switch transistor, whose gate is connected to the first gate node, is provided. A gate path includes a gate resistor. The driver circuit is configured so that, during a switching process of the power switch, the gate path is temporarily short-circuited either via the charging path or the discharging path, to increase the slope of the switching behavior of the power switch.

A switching circuit includes: a normally-off junction field-effect GaN transistor including source, drain, and gate terminals; a drive device of one output type electrically connected to the gate terminal; a first rectifier, between the source terminal and the gate terminal, including an anode on a source terminal side and a cathode on a gate terminal side; a capacitor between a cathode side of the first rectifier and the drive device; a first resistor between the capacitor and the drive device; a second resistor, one side of the second resistor being connected to the drive device, another side of the second resistor being connected between the cathode side of the first rectifier and the capacitor; and a second rectifier including an anode on a capacitor side and a cathode on a drive device side. No resistor is provided between the cathode side of the second rectifier and the drive device.