A bidirectional heterojunction transistor includes first and second conduction electrodes, first and second gates between the conduction electrodes, and first and second reference electrodes between the gates. The transistor further includes a superposition of semiconductor layers, including channel zones that are vertically in line with the gates, a first conduction zone between the first conduction electrode and the first channel zone, and a second conduction zone between the second conduction electrode and the second channel zone. The superposition of semiconductor layers also includes a third conduction zone that is separated from the first and second conduction zones by the first and second channel zones, respectively, and a first electrical connection that is connected to the third conduction zone and to the first reference electrode.

According to one embodiment, an electronic circuit includes a plurality of first transistors, a control circuit, a sample hold circuit and a calculation circuit. The control circuit selectively performs a first operation and a second operation, the first operation supplying a driving control signal to a gate terminal of a semiconductor switching element using the plurality of first transistors, and the second operation supplying a pulse current for measurement to the gate terminal using part of the plurality of first transistors. The sample hold circuit samples a voltage of the gate terminal during a period in which the pulse current is supplied to the gate terminal in the second operation. The calculation circuit calculates a gate resistance of the semiconductor switching element based on the sampled voltage.

A power conversion apparatus includes positive-side and negative-side switching elements, positive-side and negative-side gate drive circuits, and a gate signal controller. The positive-side switching element is disposed between a positive-side direct-current bus and an output node. The negative-side switching element is disposed between a negative-side direct-current bus and the output node. The positive-side and negative-side gate drive circuit are configured to turn on and off the positive-side and negative-side switching elements, respectively. The gate signal controller is configured to transmit to the positive-side and negative-side gate drive circuits gate signals to instruct turning on and off the positive-side and negative-side switching elements. The gate signal controller is configured to, when a short circuit between the positive-side direct-current bus and the negative-side direct-current bus is detected, transmit to the positive-side gate drive circuit a first gate signal and transmit to the negative-side gate drive circuit a second gate signal.

Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed.

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

Apparatus and methods for multi-gate radio frequency (RF) switches are disclosed herein. The RF switches use various layout design techniques to improve figure of merit (FOM). Examples of such techniques include using only two field-effect transistors (FETs) in series to maintain shorter fingers for lower metal resistance, placing a body contact on only one side of the RF switch layout, implementing metallization with reduced coupling from input to output, and/or providing air gaps to improve high frequency performance.

A unidirectional power switch includes: a normally-on switch device having a normally-on gate, a source, and a drain; a normally-off switch device having a normally-off gate, a source, and a drain, the drain of the normally-off switch device being electrically connected to the source of the normally-on switch device in a cascode configuration; a first source terminal electrically connected to the source of the normally-off switch device; a second source terminal electrically connected to the source of the normally-on switch device; and a drain terminal electrically connected to the drain of the normally-on switch device. The unidirectional power switch is configurable as either a normally-off unidirectional switch or a normally-on unidirectional switch, depending on a configuration of external gate driver connections to the source terminals. Additional power switch embodiments and related methods of configuring the power switches are described, including a configurable bidirectional power switch.

This disclosure is directed to a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material, and a second MOSFET formed in the semiconductor material, wherein the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, wherein the first MOSFET and the second MOSFET include a common drain node and a common source node, and wherein the first MOSFET and the second MOSFET define different transfer characteristics.

The field effect transistor (FET) of the present subject matter comprises a bottom gate electrode, a bottom gate dielectric provided on the bottom gate electrode, a channel layer provided on the bottom gate dielectric. A top portion comprising a source electrode, a drain electrode, a top gate electrode provided, and a top dielectric layer is provided on the channel layer. The channel layer forms Schottky barriers at points of contact with the source and the drain electrode. A back-gate voltage varies a height and a top-gate voltage varies a width of the Schottky barrier. The FET can be programmed to work in two operating modes-tunnelling (providing low power consumption) and thermionic mode (providing high performance). The FET can also be programmed to combine the tunnelling and thermionic mode in a single operating cycle, yielding high performance with low power consumption.