A level-shifter is provided with a first transistor and a second transistor. The first transistor functions to discharge an internal node responsive to an assertion of an inverted input signal to a first power supply voltage. A second transistor functions to discharge an inverted level-shifter output signal responsive to an assertion of an input signal to the first power supply voltage. An inverter inverts the inverted level-shifter output signal to form a level-shifter output signal that is asserted to a second power supply voltage responsive to the assertion of the input signal.

The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

A repeater for open-drain bus communication and a system including the same is provided. The repeater includes at least one repeating unit having an A-side terminal connected to an A-side open-drain bus, and a B-side terminal electrically connected to a B-side open-drain bus. The repeater has a first mode to receive a signal at the A-side and to produce a signal at the B-side. The repeating unit includes a B-side accelerator element connected to the B-side terminal. The repeating unit when in a first mode includes a first control unit to, control the B-side accelerator element to pull up a voltage at the B-side when the voltage at the A-side surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side when the voltage at the B-side surpasses a second threshold voltage.

A signal driver circuit includes a first inversion driver, a second inversion driver and an emphasis driver. The first inversion driver is configured to receive a first signal, and output a second signal by inversion-driving the first signal. The second inversion driver is configured to receive the second signal, and output a third signal by inversion-driving the second signal. The emphasis driver is configured to receive the third signal, inversion-drive the third signal, and combine the inversion-driven signal to the first signal.

Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

This application provides an interface circuit of a vehicle-mounted control unit comprising an H-bridge circuit, an input branch, and a pull-up network. An input end of the H-bridge circuit is connected to a controller 240, and an output end of the H-bridge circuit is connected to an interface port IO of the interface circuit. A first end of the input branch is connected to the interface port IO, and a second end of the input branch is connected to the controller.

The present application discloses a dual-port SRAM having two ports. On a layout, pass gates connecting to the two ports are disposed near pull down transistors of corresponding memory nodes. A cell layout structure of the SRAM cell structure is centrosymmetric. In a first subunit layout structure, a pass gate and a first pull down transistor share the same active region, and an active region of the other pull down transistor is disposed between active regions of the first pull down transistor and a first pull up transistor. The present application improves the symmetry of read paths of the two memory nodes from two ports thus the symmetry of read currents, therefore the variation of the electrical performance of PMOS transistors is reduced and the stability of the electrical performance of the PMOS transistors is improved.

A semiconductor memory device may include an impedance adjustment pad, a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground, a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device, a code register configured to store the generated pull-up code and the pull-down code, and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.

A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circuit including a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals and further includes a gate driver for driving a gate of the transistor, with supply inputs associated with a floating voltage domain, and each driver circuit also includes a level shift circuit for shifting the level of a logic signal from a fixed voltage domain to the floating voltage domain. A switching circuitry generates switching signals in a fixed voltage domain for controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit.

A data communication system has a first data communication circuit for outputting a clock signal to a clock signal line, receiving data input from a data signal line, and outputting data as open drain output to the data signal line, a second data communication circuit for receiving input of a clock signal from the clock signal line, receiving input of data from the data signal line, and outputting data as open drain output to the data signal line, a first pull-up resistor connected between the data signal line and the wiring of a power supply potential, a second pull-up resistor for selectively pulling up the data signal line, and a pull-up control circuit that is connected to the second pull-up resistor, and strengthens pull-up of the data signal line at least in response to a clock signal.