An output stage circuit includes a first operational amplifier, a second operational amplifier, a switch circuit, a clamp circuit and at least one pull-low transistor. The first operational amplifier is operated in a first voltage domain. The second operational amplifier is operated in a second voltage domain. The switch circuit is coupled to the first operational amplifier and the second operational amplifier. The clamp circuit is coupled between the switch circuit and a plurality of output terminals of the output stage circuit. The at least one pull-low transistor is coupled to the switch circuit.

A level shifter circuit included in a computer system may include bootstrap and feedback nodes. The level shifter circuit may discharge the feedback node in response to high-going transition on a received input signal generated using a first power supply signal. The level shifter circuit may also increase a voltage level of the bootstrap node in response to the high-going transition and charge the bootstrap node, in response to the discharge of the feedback node, to a voltage level of a second power supply signal that is different than a voltage level of the first power supply signal. The level shifter circuit may generate an output signal using the voltage levels of the feedback node and the second power supply signal.

A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

A current mode logic buffer device for suppressing electromagnetic interference includes two output ports and three or more sets of current mode logic buffers. First, second, and third current mode logic buffers respectively generate first, second, and third clock signals in response to first, second, and third differential input signals. The second differential input signal is delayed by a time difference from the first differential input signal, and the third differential input signal is delayed by the time difference from the second differential input signal. The output ports receive the first clock signal, the second clock signal, and the third clock signal, and output a full clock signal. A signal generating method for suppressing electromagnetic interference is also provided.

Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

A wireless sensor circuit and sensor tag in which the output is directly converted to a frequency response. The sensor circuit includes a buffer transistor having gate, source and drain terminals configured as a source-follower, a gate resistor connected to the gate terminal of the buffer transistor, a supply voltage connected to the drain terminal of the buffer transistor, and an active load element and a capacitive load element connected to the source terminal of the buffer transistor. An input signal having an input frequency is applied to the buffer transistor via the gate resistor and an output signal is generated at the source terminal of the buffer transistor. The output frequency represents a response of the sensor circuit.

A capacitive-coupled level shifter includes: an input having a positive input terminal and a negative input terminal, the input configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive divider circuit comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal of the comparator circuit. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of the modulated signal. A level shifter system which includes the capacitive-coupled level shifter is also described.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

A receiver circuit includes a first amplifier circuit, a second amplifier circuit, and a selector circuit. The first amplifier circuit is configured to receive a pair of receiving signals. The second amplifier circuit is configured to receive the pair of receiving signals. Based on a selection signal, the first amplifier circuit generates a pair of first amplifying signals according to the pair of receiving signals or the second amplifier circuit generates a pair of second amplifying signals according to the pair of receiving signals. The selector circuit is configured to output the pair of first amplifying signals or the pair of second amplifying signals according to the selection signal.