A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Voltage generators with relatively low clock feedthrough are disclosed. A voltage generator can include a charge pump with a first set of two switches arranged between two voltages, a second set of two switches arranged between one of the two voltages and an output node, and a fly capacitor connected to the first and second sets of two switches. The voltage generator can include a clock generation circuit to provide clock signals such that the two switches of the first set transition state and the two switches of the second set transition state at different times. In certain embodiments, the charge pump includes a p-type fly capacitor connected to an output node by way of an n-type transistor. In some embodiments, a level shifter can generate a level shifted clock signal for the charge pump and includes cross coupled transistors to receive a regulated voltage provided to the voltage generator.

A multiplexing latch circuit includes first, second, and third tristate inverters and an inverter. The first tristate inverter includes an output terminal and an input terminal coupled to a first data line, the second tristate inverter includes an output terminal and an input terminal coupled to a second data line, and the third tristate inverter includes an input terminal and an output terminal. The first inverter includes an input terminal coupled to the output terminals of each of the first, second, and third tristate inverters, an output terminal coupled to the input terminal of the third tristate inverter, and is configured to generate an output signal based on data received on one of the first data line or the second data line.

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

A buffer output circuit, a driving method thereof and a memory apparatus are provided. The memory apparatus includes a memory array and the buffer output circuit including a first output stage circuit and a second output stage circuit. The first output stage circuit and the second output stage circuit receive the data signal at the same time and are both coupled to the data output terminal outputting a data output signal. The second output stage circuit receives a feedback signal from the first output stage circuit. During a pre-charging-discharging period, the first output stage circuit performs a voltage pre-raising operation or a voltage pre-decreasing operation on the data output signal based on the data signal, and the second output stage circuit keeps the level of the data output signal changing based on the feedback signal until the state transition of the data output signal is completed.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

The present disclosure provides a level-shift circuit and a display device. The level-shift circuit includes a logic setting unit, a control unit, a first field effect transistor, a second field effect transistor, and an over-current protection module. An input terminal of the logic setting unit is input with an initial signal. An output terminal of the logic setting unit is connected with an input terminal of the control unit. The over-current protection module is configured to reduce a resistance of the level-shift circuit when the level-shift circuit is in an initial stage, and increase the resistance of the level-shift circuit when the level-shift circuit is in a working stage.

Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.