A calibration circuit includes a reference resistor leg, a calibration code generation circuit, and an emphasis circuit. The reference resistor leg is coupled to an external reference resistor through a reference resistor node, and changes a voltage level of the reference resistor node based on a calibration code. The emphasis circuit accelerates a voltage level change of the reference resistor node based on the calibration code.

An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

A p.sup.-type isolation region is provided at a part between a p-type ground region and a circuit region (a high potential region and an intermediate potential region) in an n-type well region. The p.sup.-type isolation region is electrically connected with a H-VDD pad and an n.sup.+-type drain region of a HVNMOS. The p.sup.-type isolation region has between n.sup.+-type pickup connect regions and between n.sup.+-type drain regions of two of the HVNMOSs, a protruding part (a T-shaped part, an L-shaped part, a partial U-shaped part) or an additional part that protrudes toward a p-ground region.

An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.

A bias current circuit which includes: a main unit including first PMOS and NMOS transistors constituting a first current path, and second PMOS and NMOS transistors constituting a second current path together with a first resistor; an output unit; and a supply voltage adapting unit including a third MOS transistor, a pull-up current source and a pull-down current source. The third MOS transistor is connected between a first node to which gates of the first and second PMOS transistors are connected and a second node to which drains of the second NMOS and PMOS transistors are connected. The pull-up current source is mirrored to the first PMOS transistor and configured to provide a current equal to a current provided by the pull-down current source. The bias current circuit has an operating voltage range encompassing low-voltage band such that it is operable at high and low voltages.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.

A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.

A multiphase serialization system for a voltage-mode transmitter includes a N-to-one stage driven by a N-phase input clock, a phase alignment unit driven by the N-phase input clock being operated to generated interpolated sampling clock signals by adjusting a plurality of reference clock signals provided to the phase alignment unit based on the N-phase input clock, and a preceding multiplexing stage driven by the interpolated sampling clock signals configured to receive incoming data streams and to output phase aligned data streams to the N-to-one stage.