An output buffer circuit includes an output terminal, a transistor, and a resistor. The transistor includes a first terminal coupled to the output terminal, a second terminal coupled to a ground rail, and a third terminal coupled to an output signal source. The resistor includes a first terminal coupled to a fourth terminal of the transistor, and a second terminal coupled to the ground rail.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

A logic cell, including a first capacitor connected between an application node for applying a supply voltage of the cell and a floating node for providing an output logic signal of the cell, and, connected in parallel with the first capacitor, an association in series of a second capacitor and a first variable-resistance element, the first variable-resistance element including a control electrode connected to an application node for applying a first input logic signal of the cell.

A logic cell, including a first capacitor connected between an application node for applying a supply voltage of the cell and a floating node for providing an output logic signal of the cell, and, connected in parallel with the first capacitor, an association in series of a second capacitor and a first variable-resistance element, the first variable-resistance element including a control electrode connected to an application node for applying a first input logic signal of the cell.

An output buffer circuit includes an output terminal, a transistor, and a resistor. The transistor includes a first terminal coupled to the output terminal, a second terminal coupled to a ground rail, and a third terminal coupled to an output signal source. The resistor includes a first terminal coupled to a fourth terminal of the transistor, and a second terminal coupled to the ground rail.

An output buffer circuit includes an output terminal, a transistor, and a resistor. The transistor includes a first terminal coupled to the output terminal, a second terminal coupled to a ground rail, and a third terminal coupled to an output signal source. The resistor includes a first terminal coupled to a fourth terminal of the transistor, and a second terminal coupled to the ground rail.

Apparatus and associated methods related to a three dimensional integrated logic circuit that includes a columnar active region. Within the columnar active region resides an interdigitated plurality of semiconductor columns and conductive columns. A plurality of transistors is vertically arranged along each semiconductor column, which extends from a bottom surface of the columnar logic region to a top surface of the columnar logic region. The plurality of transistors are electrically interconnected so as to perform a logic function and to generate a logic output signal at a logic output port in response to a logic input signal received at a logic input port. Each of the plurality of conductive columns is adjacent to at least one of the plurality of semiconductor columns and extends along a columnar axis to one or more interconnection layers at the top and/or bottom surfaces of the columnar active layer.

A line driver circuit is configured to provide a high spurious free dynamic range output and includes first and second output transistors and a control circuit. The first output transistor is controllable to pull an output node to a logic high state, and the second output transistor is controllable to pull the output node to a logic low state. The first control circuit is connected to a control input of the first output transistor and configured to establish a control signal at the control input of the first output transistor while the second output transistor is in a low impedance operating state to reduce an imbalance in turn-on delay between the first output transistor and the second output transistor.

A logic cell, including a first capacitor connected between an application node for applying a supply voltage of the cell and a floating node for providing an output logic signal of the cell, and, connected in parallel with the first capacitor, an association in series of a second capacitor and a first variable-resistance element, the first variable-resistance element including a control electrode connected to an application node for applying a first input logic signal of the cell.