Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of C.sub.PP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.

A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase.

A semiconductor device includes a 3-input NOR decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.

A transmitter controls the fall time on an open-drain link including multiple components. The transmitter includes an input driver to receive data and transmit the data on the open-drain link, thereby activating the open-drain link. The transmitter also includes a feedback mechanism to keep track of a pad when the open-drain link is activated and to determine when the pad reaches a predetermined amount of a supply voltage. When the pad reaches the predetermined amount of a supply voltage, the feedback mechanism triggers an appropriate main pull-down driver to control the fall time.

A transmitter controls the fall time on an open-drain link including multiple components. The transmitter includes an input driver to receive data and transmit the data on the open-drain link, thereby activating the open-drain link. The transmitter also includes a feedback mechanism to keep track of a pad when the open-drain link is activated and to determine when the pad reaches a predetermined amount of a supply voltage. When the pad reaches the predetermined amount of a supply voltage, the feedback mechanism triggers an appropriate main pull-down driver to control the fall time.

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.