A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of M.sub.x layer interconnects on an M.sub.x layer extending in a first direction over the first and second subcells. A first subset of the first set of M.sub.x layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of M.sub.x layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of M.sub.x layer interconnects on an M.sub.x layer extending in a first direction over the first and second subcells. A first subset of the first set of M.sub.x layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of M.sub.x layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

A table-based state machine is improved by reducing critical dependence path. In one aspect, all current states for a given input are read from a state table circuit, and the next state and output are then selected therefrom by an output multiplexer based on the current state, removing dependence on the current state from the table read, and allowing the read(s) to be pipelined. In a further aspect, multiple input units are configured to operate on multiple inputs in parallel, with each input unit propagating its state table circuit for its current input to the next downstream input unit. Each downstream input unit is configured to use the propagated state table circuit to provide the state table circuit reads to the proper output multiplexer input. The number of possible output states for a given input may be dynamically reduced, reducing the size of the output multiplexer selecting the next state.

An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.

Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.

Embodiments provide a method for data storage and comparison, a storage comparison circuit device, and a semiconductor memory. The storage comparison circuit device includes a latch and a comparator. The latch is configured to latch inputted first input data and output first output data and second output data. The first output data are the same as the first input data, whereas the second output data are different from the first input data, wherein the first output data and the second output data are respectively inputted into the comparator. The comparator is configured to receive second input data, the first output data and the second output data, and to output a comparison result. By using modular structures of the latch and the comparator, device data can be simplified for the latch and the comparator, chip area can be reduced, calculation amount can be reduced, and efficiency of data comparison can be improved.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

A table-based state machine is improved by reducing critical dependence path. In one aspect, all current states for a given input are read from a state table circuit, and the next state and output are then selected therefrom by an output multiplexer based on the current state, removing dependence on the current state from the table read, and allowing the read(s) to be pipelined. In a further aspect, multiple input units are configured to operate on multiple inputs in parallel, with each input unit propagating its state table circuit for its current input to the next downstream input unit. Each downstream input unit is configured to use the propagated state table circuit to provide the state table circuit reads to the proper output multiplexer input. The number of possible output states for a given input may be dynamically reduced, reducing the size of the output multiplexer selecting the next state.

A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer B.sub.m outputs an m-th input signal when the signal levels of both an m-th control signal C.sub.m and an n-th control signal C.sub.n of M control signals are significant, and the m-th pre-stage buffer B.sub.m enters into a high-impedance state when the signal level of at least one of the m-th control signal C.sub.m and the n-th control signal C.sub.n is non-significant. The output buffer B.sub.out sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.