A motor controller system that includes an analog switch multiplexer system is disclosed. Specific implementations include a plurality of field effect transistors (FETs) that may be configured to be operatively coupled with one or more phases of a motor. Each of the plurality of FETs may include a gate, an analog switch multiplexer coupled with each of the gates of the plurality of FETs and with an analog output, and a digital control block coupled with the analog switch multiplexer that may be configured to send a multiplexer select control signal to the analog switch multiplexer in response to receiving a serial peripheral interface signal.

Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

A dynamic bias analog vector-matrix multiplication operation circuit and an operation control method therefor. The dynamic bias analog vector-matrix multiplication operation circuit comprises: positive value weight columns (10.sub.1-10.sub.N), constant columns (20.sub.1-20.sub.M) and subtractors (30.sub.1-30.sub.N), wherein the number of the subtractors is equal to the number of the positive value weight columns, the subtractors are correspondingly connected to the positive value weight columns on a one-to-one basis, and the number of the constant columns is less than the number of the positive value weight columns; minuend input ends of the subtractors are correspondingly connected to output ends of the positive value weight columns, subtrahend input ends thereof are connected to output ends of the constant columns, and output ends thereof output operation results; and subtrahend input ends of a plurality of subtractors are connected to the same constant column. Before a weight is written in a programmable semiconductor device, a constant positive value is added to each element in a weight array to obtain a weight array to be configured, said weight array is written in a positive value weight column, and the constant positive value is written in a constant column. Therefore, a negative value weight column does not need to be set, such that the circuit structure can be simplified.

A dynamic bias analog vector-matrix multiplication operation circuit and an operation control method therefor. The dynamic bias analog vector-matrix multiplication operation circuit comprises: positive value weight columns (10.sub.1-10.sub.N), constant columns (20.sub.1-20.sub.M) and subtractors (30.sub.1-30.sub.N), wherein the number of the subtractors is equal to the number of the positive value weight columns, the subtractors are correspondingly connected to the positive value weight columns on a one-to-one basis, and the number of the constant columns is less than the number of the positive value weight columns; minuend input ends of the subtractors are correspondingly connected to output ends of the positive value weight columns, subtrahend input ends thereof are connected to output ends of the constant columns, and output ends thereof output operation results; and subtrahend input ends of a plurality of subtractors are connected to the same constant column. Before a weight is written in a programmable semiconductor device, a constant positive value is added to each element in a weight array to obtain a weight array to be configured, said weight array is written in a positive value weight column, and the constant positive value is written in a constant column. Therefore, a negative value weight column does not need to be set, such that the circuit structure can be simplified.

A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

An electrical system may include a mounting surface, a component configured for connection with the mounting surface and configured to move relative to the mounting surface, and/or an orientation sensor configured to determining an orientation of the component relative to the mounting surface. The orientation sensor may include a first sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected, at least indirectly, to the mounting surface, and a second sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected to move with the component. The orientation sensor may include an electronic controller. The electronic controller may be configured to compare first information from the first sensor to second information from the second sensor to determine the orientation of the component relative to the mounting surface.

An electrical system may include a mounting surface, a component configured for connection with the mounting surface and configured to move relative to the mounting surface, and/or an orientation sensor configured to determining an orientation of the component relative to the mounting surface. The orientation sensor may include a first sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected, at least indirectly, to the mounting surface, and a second sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected to move with the component. The orientation sensor may include an electronic controller. The electronic controller may be configured to compare first information from the first sensor to second information from the second sensor to determine the orientation of the component relative to the mounting surface.

Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.