The present invention is directed to methods and compositions for generating a pool of oligonucleotides. The invention finds use in preparing a population or subpopulations of oligonucleotides in solution. The pool of oligonucleotides finds use in a variety of nucleic acid detection and/or amplification assays.

A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects, in synchronization with a second dock signal having a phase leading a first clock signal, a logic level of an input signal and drives, in synchronization with the first clock signal, the output node to a second logic level according to the logic level of the input signal.

A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in response to a configuration signal, the output circuit between the latch mode and the pass-through mode.

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10.sup.19 (atoms/cm.sup.3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10.sup.19 (atoms/cm.sup.3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Provided is a logic circuit comprising: a switch portion that includes one or more switching devices configured to be turned on and off in accordance with an input signal and is configured to generate an output signal with a logical value according to an operating state of the switching devices; and a clamp portion configured to clamp a voltage of the output signal, of a case where the logical value of the output signal is logic H. The switch portion may be arranged between an output line and a reference potential line, and the clamp portion may be arranged in parallel with the switch portion, between the output line and the reference potential line. The logic circuit may include a current suppression portion configured to suppress a current flowing through the clamp portion, when the logical value of the output signal is logic H.