An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.

A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.

An integrated circuit comprising a field programmable gate array including a plurality of logic tiles physically organized in at least one row and at least one column and wherein each logic tile (i) is electrically coupled and physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes (a) logic circuitry, (b) memory, and (c) a configurable switch interconnect network which is electrically coupled to the memory, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and organized into a plurality of switch matrices and wherein the plurality of switch matrices are arranged in a plurality of stages. In one embodiment, each logic tile of the plurality of logic tiles is capable of communicating, during operation, with at least one other logic tile of the plurality of logic tiles.

According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

An integrated circuit with a clock distribution network is provided. The clock distribution network may include configurable clock routing paths linking a clock source to one or more clock tree roots and may also include fixed clock routing paths linking the clock tree roots to corresponding leaf nodes. Both the configurable clock routing paths and the fixed clock routing paths can be implemented using an array of logic regions, where each logic region includes a clock switching box, a horizontal routing segment, a vertical routing segment, and associated logic circuitry. The configurable routing paths may include horizontal/vertical routing segments with bidirectional tristate buffers. The fixed routing paths may include horizontal/vertical routing segments with unidirectional inverters that are configured to form an H-tree.

A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

An integrated circuit comprising a plurality of switch matrices wherein the plurality of switch matrices are arranged in stages including (i) a first stage, configured in a hierarchical network (for example, a radix-4 network), (ii) a second stage configured in a hierarchical network (for example, a radix-2 or radix-3 network) and coupled to switches of the first stage, and (iii) a third stage configured in a mesh network and coupled to switches of the first and/or second stages. In one embodiment, the third stage of switch matrices is located between the first stage and second stage of switch matrices; in another embodiment, the third stage is the highest stage.

An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a third terminal connected to the second terminal, and a fourth terminal; a first wiring line connected to the first terminal of the anti-fuse element; and a drive circuit configured to supply a plurality of potentials to the first terminal of the anti-fuse element, the drive circuit being connected to the first wiring line, the potentials being different from each other.