Examples herein describe techniques for adapting a multiplier array (e.g., a systolic array implemented in a processing core) to perform different dot products. The processing core can include data selection logic that enables different configurations of the multiplier array in the core. For example, the data selection logic can enable different configurations of the multiplier array while using the same underlying hardware. That is, the multiplier array is fixed hardware but the data selection can transmit data into the matrix multiplier such that it is configured to perform different length dot products, perform more dot products in parallel, or change its output precision. In this manner, the same underlying hardware (i.e., the multiplier array) can be reconfigured for different dot products which can result in much more efficient use of the hardware.

A method of integrated circuit includes: providing a non-volatile memory circuit for securely and permanently recording and protecting key data content having Y bits; providing a programmable memory circuit for storing user configuration data content having X bits greater than Y bits; converting the user configuration data content having X bits into user configuration key content having Y bits; comparing the user configuration key content having Y bits with the key data content having Y bits; selecting fallback configuration data content having X bits as output data when the user configuration key content does not match the key data content; selecting the user configuration data content having X bits as the output data when the user configuration key content matches the key data content; and receiving the output data of the decision circuit and performing at least one corresponding capability operation according to the output data.

A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.

An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.

An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.

A filter device includes an unbalanced terminal, balanced terminals, and first and second resonant circuits. The first resonant circuit is connected to the unbalanced terminal. The second resonant circuit is connected to the balanced terminals and electromagnetically coupled with the first resonant circuit. The first resonant circuit includes a resonator in which an inductor and a capacitor are connected in parallel between the unbalanced terminal and a reference potential. The second resonant circuit includes a resonator including an inductor connected between the balanced terminals and capacitors connected in series between the balanced terminals.

A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.

A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.