A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.

A redriver chip comprising: pre-stage transmission pin sets, pre-stage reception pin sets, post-stage transmission pin sets, post-stage reception pin sets and selectors. The pre-stage transmission pin sets and the pre-stage reception pin sets are disposed in alternating arrangement, and the post-stage transmission pin sets and the post-stage reception pin sets are disposed in alternating arrangement. The amount of the post-stage transmission pin sets is an integral multiple of the amount of pre-stage reception pin sets, and the amount of the pre-stage reception pin sets is an integral multiple of the pre-stage transmission pin sets. Each of the selectors is connected to one of the pre-stage reception pin sets and integral multiple amount of the post-stage transmission pin sets, or is connected to one of the pre-stage transmission pin sets and integral multiple amount of the post-stage reception pin sets.

In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

A pin state configuration circuit, a method for configuring pin states and an electronic device for configuring pin states are provided. The pin state configuration circuit includes a configured resistor load, a voltage sampling unit, and a comparator. The voltage sampling unit supplies a reference voltage to the configured resistor load by using a first or second configuration pin, and respectively samples voltages of the first and second configuration pins. The comparator calculates a first voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, calculates a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, and determines a corresponding pin configuration state based on the first and second voltage ratios. In this way, N×N pin configuration states may be obtained by configuring two configuration pins.

A multiplexer includes a first inverter for receiving and inverting first data, a second inverter for receiving and inverting second data, and a first driver connected to an output of the first inverter and to an output of the second inverter. The first driver is configured to output the first data or the second data as output data.

A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.

One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.

In certain aspects, an apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, wherein the toggle circuit is configured to toggle a logic state at the output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal, and couple the selected one of the first input and the second input to the output of the multiplexer.

Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

The present technology includes a memory device which includes a plurality of planes in which data is stored, a peripheral circuit configured to perform operations on the plurality of planes, micro-control circuits configured to control the peripheral circuit so that the operations on the plurality of planes are independently performed, and a memory manager including a control memory in which different control codes for controlling the peripheral circuit are stored, and configured to output the control codes to the micro-control circuits, wherein the memory manager is configured to sequentially output a selected control code among the control codes to the micro-control circuits respectively corresponding to the planes.