Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit.

A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

According to an aspect of an embodiment, a method of array source code partitioning and topology determination may include determining an optimum topology of an array of field programmable gate array (FPGA) devices based on a processing specification. The method may include automatically performing the best-effort partitioning on a default topology of the array of FPGA devices. The method may include partitioning parallel and serial source code among the FPGA devices mapped into optimum topology or the default topology. The method may include mapping a virtual topology onto a fixed physical topology of the array of FPGA devices. The method may include presenting computing resources of the array of FPGA devices to a host or to an entire application as a larger FPGA or as software-defined computing resources.

According to one embodiment, in a semiconductor device, a connection block includes multiple unit configurations, in each of which a first line extends along a first direction. A second line is placed above the first line and extends along a second direction which intersects with the first direction. A first variable resistance element has one end electrically connected to the first line and another end electrically connected to the second line. The third line is placed above the second line and extends along the first direction. A second variable resistance element has One end electrically connected to the second line and another end electrically connected to the third line. A fourth line is placed above the third line. The fourth line extends along the second direction. A third variable resistance element has one end electrically connected to the third line and another end electrically connected to the fourth line.

A wake-up circuit, a wake-up method and a non-transitory computer-readable storage medium are disclosed. The wake-up circuit includes a wake-up module (11) and a main control module (12). The wake-up module (11) is connected to a wake-up source and is configured to detect a wake-up signal sent by the wake-up source, and to forward the wake-up signal to the main control module (12), one or more wake-up sources being provided. The main control module (12) is connected to the wake-up module (11) and is configured to receive the forwarded wake-up signal, one main control modules (12) being provided.

Various embodiments of the present technology may provide methods and apparatus for reordering signals that are generated by a sensor. The apparatus may receive the generated signals in the form of a plurality of X-bit input signals and generate a plurality of output signals according to an exemplary reordering scheme. The apparatus may perform the exemplary reordering scheme based on one or more states of a state machine.

Various embodiments of the present technology may provide methods and apparatus for reordering signals that are generated by a sensor. The apparatus may receive the generated signals in the form of a plurality of X-bit input signals and generate a plurality of output signals according to an exemplary reordering scheme. The apparatus may perform the exemplary reordering scheme based on one or more states of a state machine.

Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.