A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements, wherein the processor is configured to: receive designation of a processing group including a series of plural kinds of processing; acquire management data decided for each processing group, the management data designating plural pieces of reconfiguration data each designating connection between elements in a corresponding one of the plural reconfiguration regions so that the designated processing group is performed; acquire the plural pieces of reconfiguration data designated by the acquired management data; change connection between elements in the plural reconfiguration regions in accordance with the designation by the acquired plural pieces of reconfiguration data; and when connection between elements is changed in accordance with designation by the plural pieces of reconfiguration data, in a case where designation by at least one of the acquired plural pieces of reconfiguration data does not require change of connection in a corresponding one(s) of the plural reconfiguration regions, use same reconfiguration data as that used to connect the elements in the corresponding one(s) of the plural reconfiguration regions.

A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements, wherein the processor is configured to: receive designation of a processing group including a series of plural kinds of processing; acquire management data decided for each processing group, the management data designating plural pieces of reconfiguration data each designating connection between elements in a corresponding one of the plural reconfiguration regions so that the designated processing group is performed; acquire the plural pieces of reconfiguration data designated by the acquired management data; change connection between elements in the plural reconfiguration regions in accordance with the designation by the acquired plural pieces of reconfiguration data; and when connection between elements is changed in accordance with designation by the plural pieces of reconfiguration data, in a case where designation by at least one of the acquired plural pieces of reconfiguration data does not require change of connection in a corresponding one(s) of the plural reconfiguration regions, use same reconfiguration data as that used to connect the elements in the corresponding one(s) of the plural reconfiguration regions.

A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements. The processor is configured to: upon detection of an abnormality while performing processing in a state in which the elements in the reconfiguration regions are connected in accordance with reconfiguration data designating connection between the elements in the reconfiguration regions, acquire reconfiguration data designating such connection between the elements that the processing being performed is not performed; and change connection between the elements in the reconfiguration regions in accordance with the designation by the acquired reconfiguration data.

A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements. The processor is configured to: upon detection of an abnormality while performing processing in a state in which the elements in the reconfiguration regions are connected in accordance with reconfiguration data designating connection between the elements in the reconfiguration regions, acquire reconfiguration data designating such connection between the elements that the processing being performed is not performed; and change connection between the elements in the reconfiguration regions in accordance with the designation by the acquired reconfiguration data.

Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network-based apparatus to: select at least a first bitstream from a central repository based on an indicator associated with a probability of concurrent, simultaneous or future execution of the first bitstream and a second bitstream at a network node, each of the first bitstream and the second bitstream including programming information for a device at the network node, the indicator being based on an embedding matrix mapping at least a subset of bitstreams in the central repository to an N-dimensional vector of real numbers; and output the first bitstream to the network node for storage and execution upon request.

Systems and methods described herein may relate to power inlet reconfiguration of an integrated circuit device. In an embodiment, an add in card includes an integrated circuit including programmable logic circuitry. The add in card also includes any number of voltage regulators configured to supply power to the integrated circuit and a controller. The controller configures the programmable logic circuitry based on a configuration profile, determine a power level associated with the configuration profile, and adjust the plurality of voltage regulators and load switches based on the power level.

A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method.

Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.