A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. In a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs. In a second mode of operation, the first plurality of values is received via a second portion of the plurality of inputs, and the second plurality of values is received via the first portion of the plurality of inputs. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. In a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs. In a second mode of operation, the first plurality of values is received via a second portion of the plurality of inputs, and the second plurality of values is received via the first portion of the plurality of inputs. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.