The driver system according to the invention includes an infrared receiver module and a Johnson counter. The infrared receiver module receives an infrared signal and performs filtering using a low-pass filter to convert the infrared signal into a driving signal which is transmitted to the Johnson counter. Upon receiving the driving signal, the output terminals of the Johnson counter are sequentially activated to output a control signal for shifting the operation of an electrical device from one operation state to another.

A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.

This disclosure provides systems, methods, and devices for wireless communications that support configurable clock dividers for mixer operation in a radio frequency front end (RFFE). In a first aspect, an apparatus for wireless communications includes a first clock loop comprising a first plurality of latches generating a first plurality of clock signals with a corresponding first plurality of phases; and a second clock loop comprising a second plurality of latches generating a second plurality of clock signals with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal. Other aspects and features are also claimed and described.

A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit.

An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.

A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit.