A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

Nested phase-locked loops (PLLs) utilize resonators of different quality factors, oscillation frequencies, and tunability. A reference clock signal for a first PLL is based on a free running bulk acoustic wave (BAW) resonator. The first PLL utilizes an LC oscillator as a voltage controlled oscillator. A crystal oscillator supplies a reference clock signal to a second PLL. Feedback dividers of the first and second PLLs are coupled to the LC oscillator. A delta sigma modulator coupled to the loop filter of the second PLL controls the feedback divider of the first PLL. The first PLL utilizes a high update rate to ensure that the jitter power spectral density is spread over a wide frequency range. The nested PLL architecture allows the overall phase noise plot to follow that of the crystal resonator at low frequencies, the BAW resonator at mid-frequencies, and the LC resonator at high frequencies.

An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.

An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

A DLL circuit comprising a delay circuit, a phase detector and a counting control circuit. The delay circuit is configured to receive a reference clock signal, and delay the reference clock signal to output a delayed clock signal. The phase detector is configured to detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal. The counting control circuit is configured to generate a control delay signal according to the phase difference signal. The delay circuit delays the reference clock signal according to the control delay signal to output the delayed clock signal. When the counting control circuit is in the first mode, the counting control circuit has a first update frequency. When the counting control circuit is in the second mode, the counting control circuit has a second update frequency.